Class D analog-to-digital converter

• US 7,528,760 B2
• Filed: 01/26/2007
• Issued: 05/05/2009
• Est. Priority Date: 01/26/2007
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Forejt, Brett
• Primary Examiner(s): YOUNG, BRIAN K
• Application Number:
  US11/627,635
• Publication Number:
  US 20080180299A1
• Time in Patent Office: 830 Days
• Field of Search: 341/166, 341/155, 341/167, 341/168, 341/169, 341/170
• US Class Current: 341/166
• CPC Class Codes: G04F 10/005 Time-to-digital converters [TDC] analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60
• CPC Class Codes: H03M 1/504 using pulse width modulation

Abstract

A new analog-to-digital (ADC) circuit and architecture and the corresponding method of implementation are provided. The analog input signal is converted into a modulated pulse stream such as by a pulse-width-modulation scheme. The time-duration width of the pulses are measured by a TDC (time-to-digital converter) and converted to a digital binary representation that is directly correlated with the voltage amplitude of the analog input signal. The circuit implementation is substantially free of switches and circuit issues such as associated with sigma-delta and switched-capacitor techniques for ADC'"'"'s.

Claims

1. An analog-to-digital converter (ADC) circuit, comprising:

an ADC input node, a pulse-stream output node and N digital output nodes;

a modulated square wave converter (MSWC) connected between the ADC input node and pulse-stream output node;

a time to digital converter (TDC) connected between the pulse-stream output node and the N digital output nodes, where N is a number greater than one; and

the MSWC comprising a ramp signal generator operable to help establish a modulated pulse stream at the pulse-stream output node.

2. The ADC circuit of claim 1 wherein the MSWC further comprises a comparator;

the ramp signal generator has a ramp output node; and

the comparator has a first input node connected to the ADC input node and a second input node connected to the ramp output node; and

the comparator has an output node connected to the pulse-stream output node.

3. The ADC circuit of claim 2 wherein the ADC circuit is operable to receive a master clock;

and the ramp signal generator and TDC are both operable to generate outputs, in synchronism with the master clock.

4. The ADC circuit of claim 2 wherein the ADC circuit is operable to receive a master clock;

and the comparator is operable to output the modulated pulse stream and the TDC is operable to generate N digital outputs, both in synchronism with the master clock.

5. The ADC circuit of claim 1 wherein the TDC comprises a ring oscillator and a counter which has a first input and a second input;

and the ring oscillator comprises taps operable to generate regular, brief pulses at the counter'"'"'s first input;

the counter'"'"'s second input is connected to the pulse-stream output node; and

the counter has output nodes which are the N digital output nodes.

6. The ADC circuit of claim 2 wherein the TDC comprises an oscillator circuit and a counter which has a first input and a second input;

and the oscillator circuit is operable to generate regular, brief pulses at the counter'"'"'s first input;

the counter'"'"'s second input is connected to the pulse-stream output node; and

the counter has output nodes which are the N digital output nodes.

7. An analog-to-digital converter (ADC) circuit, comprising:

differential ADC input nodes, a pulse-stream output node and N digital output nodes;

a modulated square wave converter (MSWC) connected between the ADC input node and pulse-stream output node;

a time to digital converter (TDC) connected between the pulse-stream output node and the N digital output nodes, where N is a number greater than one; and

the MSWC comprising a ramp signal generator operable to help establish a modulated pulse stream at the pulse-stream output node.

8. The ADC circuit of claim 7 wherein the ADC is a differential circuit and the MSWC has a differential feedback circuit with inputs connected to the differential ADC input nodes;

and the differential feedback circuit has an output connected to the pulse-stream output node.

9. The ADC circuit of claim 8 wherein the differential feedback circuit has at least two stages with nested feedback.

10. The ADC circuit of claim 8 wherein the differential feedback circuit further comprises only passive elements operable to provide feedback.

11. The ADC circuit of claim 7 wherein the MSWC comprises an integrator circuit with differential outputs, and two comparators;

the ramp signal generator has a ramp output node;

the two comparators each have a first input node connected to one of the differential outputs, respectively;

the comparators each have a second input node connected to the ramp output node; and

the integrator circuit has differential inputs connected to the differential ADC input nodes, respectively.

12. The ADC circuit of claim 11 wherein the two comparators each have a comparator output node;

the MSWC further comprises a logic circuit connected to the comparator output nodes, and the logic circuit is further connected to the pulse-stream output node.

13. The ADC circuit of claim 12 wherein the logic circuit has a pair of logic feedback nodes and the integrator circuit has a pair of amplifier input nodes;

and the MSWC further comprises a pair of feedback circuits, each between a pairing of the logic feedback node and the amplifier input node.

14. The ADC circuit of claim 12 wherein the logic circuit comprises an XOR gate.

15. The ADC circuit of claim 7 further comprising one polarity bit output node in addition to the N digital output nodes.

16. A method to convert an analog signal into digital form comprises the steps of:

generating a ramp signal;

converting the analog signal to a modulated pulse wave;

providing a counter with pulses from an oscillator and with said modulated pulse wave, the counter producing N digital bits, where N is a number greater than one; and

configuring a modulated square wave converter (MSWC) to generate the modulated pulse wave by comparing the ramp signal with the analog signal.

17. The method of claim 16 further comprising the step of using a PWM (pulse width modulation) scheme to generate the modulated pulse wave.

18. The method of claim 16 further comprising the step of applying feedback in the step of converting the analog signal to the modulated pulse wave.

19. An analog-to-digital converter (ADC) circuit, comprising:

an ADC input node, a pulse-stream output node and N digital output nodes;

a modulated square wave converter (MSWC) connected between the ADC input node and pulse-stream output node;

a time to digital converter (TDC) connected between the pulse-stream output node and the N digital output nodes, where N is a number greater than one; and

the MSWC and TDC both responsive to a same master clock signal, wherein the MSWC is operable to generate a modulated pulse stream at the pulse-stream output node.