System and method for improving dynamic performance of a circuit

• US 7,538,701 B2
• Filed: 06/09/2007
• Issued: 05/26/2009
• Est. Priority Date: 06/08/2006
• Status: Expired due to Fees

• Current Assignee: Cosmic Circuits Pvt., Ltd. (Cadence Group)
• Original Assignee: Cosmic Circuits Pvt., Ltd. (Cadence Group)
• Inventors: Teeka Srinivasa Shetty, Venkatesh, Chakravarthy, Srinivasan, Easwaran, Prakash, Bhowmik, Prasenjit, Krishnan, Sundararajan, Kali Bhattacharya, Prasun, Kumar Ghosh, Sanjeeb, Khatri, Mukesh, Chakkirala, Sumanth, Lakshminarayanan, Chandrashekar
• Primary Examiner(s): Nguyen; Linh V
• Application Number:
  US11/760,746
• Publication Number:
  US 20070285297A1
• Time in Patent Office: 717 Days
• Field of Search: 341/131, 341/143, 341/118, 341/120, 341/126, 341/155
• US Class Current: 341/131
• CPC Class Codes: H03M 1/0641 the dither being a random signal
• CPC Class Codes: H03M 1/12 Analogue/digital converters H03M1/001 – H03M1/10 take precedence

Abstract

A system and method for improving the dynamic performance in an analog-to-digital converter (ADC) by randomizing the differential mismatch. The differential mismatch in an input analog signal is randomized by flipping the input signal and output signal randomly.

Claims

1. A method for improving the dynamic performance of a circuit, the method comprising the steps of:

randomly multiplying an input signal of the circuit with a pseudo random bit sequence in an input stage to produce a modified input signal;

processing the modified input signal in the circuit to generate a modified output signal; and

multiplying the modified output signal with the pseudo random bit sequence used at the input stage to produce a final output signal, whereby even harmonics in the final output signal are randomized.

2. The method according to claim 1, wherein the pseudo random bit sequence comprises a random sequence of positive and negative values.

3. The method according to claim 2, wherein the positive values are +1 and the negative values are −

1.

4. The method according to claim 1, wherein the circuit is an analog-to-digital convener (ADC) circuit.

5. The method according to claim 1, wherein the circuit is a switched capacitor circuit.

6. The method of claim 1 further comprising:

removing noise due to offset in the circuit.

7. A system for improving the dynamic performance of a circuit, the system comprising:

a pseudo-random bit sequence generator for generating a pseudo random bit sequence;

a first multiplier for multiplying an input analog signal with said pseudo random bit sequence to provide a modified analog input signal;

a circuit core for receiving said modified analog input signal as input and for converting said modified analog input signal to a modified digital output signal; and

a second multiplier for multiplying said modified digital output signal with said pseudo random bit sequence to generate a final output signal.