Delay line with delay cells having improved gain and in built duty cycle control and method thereof
First Claim
1. A delay cell, the delay cell comprising:
- a current source including a drain, a gate and a source, wherein the gate of the current source receives a voltage bias signal;
a first transistor including a drain, a gate, and a source, wherein the drain of the first transistor is electrically connected to the drain of the current source, the gate of the first transistor receives an input clock signal that drives the delay cell, and the source of the first transistor is electrically connected to a power supply terminal;
a second transistor including a drain, a gate, and a source, wherein the drain of the second transistor is electrically connected to the source of the current source, the gate of the second transistor receives the input clock signal, and the source of the second transistor is electrically connected to a ground terminal;
a third transistor including a drain, a gate, and a source, wherein the gate of the third transistor is electrically connected to the drain of the current source, and the source of the third transistor is electrically connected to the power supply terminal;
a fourth transistor including a drain, a gate, and a source, wherein the drain of the fourth transistor is electrically connected to the drain of the third transistor, the gate of the fourth transistor is coupled to an output of an another delay cell, and the source of the fourth transistor is electrically connected to the ground terminal; and
a load capacitor having a first terminal and a second terminal, wherein the first terminal is electrically connected to the drain of the current source, and the second terminal is electrically connected to the ground terminal.
1 Assignment
0 Petitions
Accused Products
Abstract
A delay line including a sequence of identical delay cells with improved gain and in built duty cycle distortion control and a method thereof is disclosed. Each delay cell of the sequence includes a current source, four transistors, and a load capacitor. A gate of the current source receives a voltage bias that controls a delay of the delay cell. A drain of the first transistor is connected to the drain of the current source. The first and second transistor gates receive an input clock signal. The second transistor drain is connected to the source of the current source. The third transistor gate and the load capacitor are also connected to the drain of the current source. The fourth transistor drain is connected to the third transistor drain. The fourth transistor gate is coupled to an output of a second consecutive delay cell for duty cycle distortion control.
-
Citations
15 Claims
-
1. A delay cell, the delay cell comprising:
-
a current source including a drain, a gate and a source, wherein the gate of the current source receives a voltage bias signal; a first transistor including a drain, a gate, and a source, wherein the drain of the first transistor is electrically connected to the drain of the current source, the gate of the first transistor receives an input clock signal that drives the delay cell, and the source of the first transistor is electrically connected to a power supply terminal; a second transistor including a drain, a gate, and a source, wherein the drain of the second transistor is electrically connected to the source of the current source, the gate of the second transistor receives the input clock signal, and the source of the second transistor is electrically connected to a ground terminal; a third transistor including a drain, a gate, and a source, wherein the gate of the third transistor is electrically connected to the drain of the current source, and the source of the third transistor is electrically connected to the power supply terminal; a fourth transistor including a drain, a gate, and a source, wherein the drain of the fourth transistor is electrically connected to the drain of the third transistor, the gate of the fourth transistor is coupled to an output of an another delay cell, and the source of the fourth transistor is electrically connected to the ground terminal; and a load capacitor having a first terminal and a second terminal, wherein the first terminal is electrically connected to the drain of the current source, and the second terminal is electrically connected to the ground terminal. - View Dependent Claims (2, 3, 4, 5, 6, 7)
-
-
8. A delay line including a sequence of delay cells, a first delay cell of the sequence being driven by a reference clock signal, and each successive delay cell of the sequence being driven by an output from a preceding delay cell, wherein each delay cell of the sequence comprises:
- a current source including a drain, a gate and a source, wherein the gate of the current source receives a voltage bias signal;
a first transistor including a drain, a gate, and a source, wherein the drain of the first transistor is electrically connected to the drain of the current source, the gate of the first transistor receives an input clock signal that drives the delay cell, and the source of the first transistor is electrically connected to a power supply terminal;
a second transistor including a drain, a gate, and a source, wherein the drain of the second transistor is electrically connected to the source of the current source, the gate of the second transistor receives the input clock signal, and the source of the second transistor is electrically connected to a ground terminal;
a third transistor including a drain, a gate, and a source, wherein the gate of the third transistor is electrically connected to the drain of the current source, and the source of the third transistor is electrically connected to the power supply terminal;
a fourth transistor including a drain, a gate, and a source, wherein the drain of the fourth transistor is electrically connected to the drain of the third transistor, the gate of the fourth transistor is coupled to an output of a second consecutive delay cell following the delay cell, and the source of the fourth transistor is electrically connected to the ground terminal; and
a load capacitor having a first terminal and a second terminal, wherein the first terminal is electrically connected to the drain of the current source, and the second terminal is electrically connected to the ground terminal. - View Dependent Claims (9, 10, 11, 12, 13, 14)
- a current source including a drain, a gate and a source, wherein the gate of the current source receives a voltage bias signal;
-
15. A method for maintaining a gain and a duty cycle of a delay cell, the delay cell comprising a first transistor, a second transistor, a third transistor, a fourth transistor, and a load capacitor, the method comprising:
- providing a discharge path for a charge stored in the load capacitor, wherein the discharge path is provided by inserting a current source between a drain of the first transistor and the drain of the second transistor, and wherein the load capacitor discharges to ground through the current source and the second transistor, wherein a source of the current source is electrically connected to the drain of the second transistor; and
providing a pull down path to an intermediate output of the delay cell based on receiving a pulse of an output of a second consecutive delay cell to the delay cell at a gate of the fourth transistor, wherein the intermediate output is received at a junction between the drain of the third transistor and the drain of the fourth transistor, wherein receiving the intermediate output is based on receiving the charge stored in the load capacitor at a gate of the third transistor.
- providing a discharge path for a charge stored in the load capacitor, wherein the discharge path is provided by inserting a current source between a drain of the first transistor and the drain of the second transistor, and wherein the load capacitor discharges to ground through the current source and the second transistor, wherein a source of the current source is electrically connected to the drain of the second transistor; and
Specification