Pick-up structure for DRAM capacitors

• US 7,554,148 B2
• Filed: 06/27/2006
• Issued: 06/30/2009
• Est. Priority Date: 06/27/2006
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Su, Yi-Nan, Yang, Chin-Sheng
• Primary Examiner(s): Jackson, Jr.; Jerome
• Assistant Examiner(s): Budd; Paul A
• Application Number:
  US11/309,131
• Publication Number:
  US 20070296010A1
• Time in Patent Office: 1,099 Days
• Field of Search: 257/301, 257/E27.091
• US Class Current: 257/301
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 29/66181 Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
• CPC Class Codes: H10B 12/0387 Making the trench
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells

Abstract

A pick-up structure for DRAM capacitors and a DRAM process are described. A substrate with trenches therein is provided, wherein the trenches include a first trench and the sidewall of each of the trenches is formed with a dielectric layer thereon. A conductive layer is formed on the surfaces of the substrate and the trenches, and then a patterned photoresist layer is formed on the conductive layer filling in the trenches and further covering the first trench. The exposed conductive layer is removed to form bottom electrodes in the trenches, and then the patterned photoresist layer is removed. A capacitor dielectric layer is formed on each bottom electrode, and then top electrodes are formed on the substrate filling up the trenches. A contact is then formed on the bottom electrode in the first trench, electrically connecting the substrate via the bottom electrode.

Claims

1. A capacitor pick-up structure, applied to a memory cell array area of a DRAM that is disposed on a substrate over a doped band in the substrate, and comprising:

a dummy capacitor in a first trench in the substrate, wherein a bottom of the first trench exposes a portion of the doped band, the dummy capacitor comprising;

a first bottom electrode on an internal surface of the first trench, electrically connecting with the doped band;

a first dielectric layer between the first bottom electrode and a sidewall of the first trench; and

a first top electrode on the first bottom electrode, filling up the first trench; and

a contact over the substrate, electrically connecting with the doped band via the dummy capacitor.

2. The capacitor pick-up structure of claim 1, which is disposed at an edge of the memory cell array area.

3. The capacitor pick-up structure of claim 1, which is disposed at a corner of the memory cell array area.

4. The capacitor pick-up structure of claim 1, wherein a top surface of the first bottom electrode is higher than or coplanar with a top surface of the substrate.

5. The capacitor pick-up structure of claim 4, wherein the contact electrically connects with the first bottom electrode at least.

6. The capacitor pick-up structure of claim 4, further comprising a first capacitor dielectric layer between the first bottom electrode and the first top electrode.

7. The capacitor pick-up structure of claim 6, wherein the first capacitor dielectric layer comprises an ONO layer.

8. The capacitor pick-up structure of claim 1, wherein a top surface of the first bottom electrode is lower than a top surface of the substrate.

9. The capacitor pick-up structure of claim 8, wherein the contact is disposed on the first top electrode.

10. The capacitor pick-up structure of claim 1, wherein a memory cell in the memory cell array area comprises:

a transistor on the substrate;

a trench capacitor in the substrate beside the transistor; and

a conductive layer on the substrate for coupling the transistor with the trench capacitor.

11. The capacitor pick-up structure of claim 10, wherein the trench capacitor is disposed in a second trench in the substrate, a bottom of the second trench exposes a portion of the doped band, and the trench capacitor comprises:

a second bottom electrode on an internal surface of the second trench, electrically connecting with the doped band;

a second dielectric layer between the second bottom electrode and a sidewall of the second trench;

a second top electrode on the second bottom electrode, filling up the second trench; and

a second capacitor dielectric layer between the second bottom electrode and the second top electrode.

12. The capacitor pick-up structure of claim 10, wherein the DRAM further comprises an isolation structure that has a portion disposed between every two adjacent trench capacitors and encroaching upon the two adjacent trench capacitors.

13. The capacitor pick-up structure of claim 12, wherein the DRAM further comprises passing gate structures on the isolation structure.

14. The capacitor pick-up structure of claim 1, further comprising an isolation structure that encroaches upon the dummy capacitor.

15. The capacitor pick-up structure of claim 14, wherein the DRAM further comprises a passing gate structure on the isolation structure that encroaches upon the dummy capacitor.