Radio frequency switch

• US 7,561,853 B2
• Filed: 01/14/2005
• Issued: 07/14/2009
• Est. Priority Date: 01/16/2004
• Status: Expired due to Fees

• Current Assignee: Eudyna Devices Inc. (Sumitomo Corporation)
• Original Assignee: Eudyna Devices Inc. (Sumitomo Corporation)
• Inventors: Miyazawa, Naoyuki
• Primary Examiner(s): Le; Lana N
• Assistant Examiner(s): HU, RUI MENG
• Application Number:
  US11/034,755
• Publication Number:
  US 20060160520A1
• Time in Patent Office: 1,642 Days
• Field of Search: 327/382, 327/389, 327/427, 327/566, 257/275, 257/401, 257/48, 455/78, 455/83, 455/82
• US Class Current: 455/83
• CPC Class Codes: H01P 1/15 by semiconductor devices
• CPC Class Codes: H03K 17/102 in field-effect transistor switches
• CPC Class Codes: H04B 1/44 Transmit/receive switching

Abstract

A switch that selectively changes radio frequency signals includes at least three FETs, which are connected in series. The source electrodes or drain electrodes arranged at an intermediate stage have a width narrower than that of the source electrodes or the drain electrodes arranged at the initial and final stages. It is thus possible to lower the parasitic capacitance to ground at the intermediate stage and to thereby realize the switch having a high handling power.

Claims

1. A switch comprising:

at least three FETs that allow radio frequency signals from one end to travel toward another end and allow the radio frequency signals from said one end to pass across all of said at least three FETs,

said at least three FETs being connected in series between a node and a ground wherein said node is connected between said one end and said another end, wherein;

a drain electrode of one of the at least three FETs arranged at an initial stage is connected to said node, and a source electrode of one of the at least three FETs arranged at a final stage is connected to the ground;

a drain electrode of one of the at least three FETs arranged at an intermediate stage is connected to a source electrode of the one of the at least three FETs arranged at the initial stage, and a source electrode of the one of the at least three FETs arranged at the intermediate stage is connected to a drain electrode of the one of the at least three FETs arranged at the final stage;

widths of both of the drain and source electrodes of the one of the at least three FETs arranged at the intermediate stage is less than the width of the drain electrode of the one of the at least three FETs arranged at the initial stage and the width of the source electrode of the one of the at least three FETs arranged at the final stage; and

means for selecting said at least three FETs to allow the radio frequency signals from said one end to travel toward said another end in the case that all of said at least three FETs are off, and allow the radio frequency signals to pass across all of said at least three FETs from said one end to the ground in the case that all of said at least three FETs are on.

2. The switch as claimed in claim 1, wherein the radio frequency switch comprises at least four FETs connected in series.

3. The switch as claimed in claim 2, wherein source and drain electrodes of one of at least four FETs arranged on intermediate stages have widths of source and drain electrodes narrower than the width of the drain electrode connected to said node and the width of the source electrode connected to the ground.

4. The switch as claimed in claim 1, wherein a total width of gate electrodes of the FETs except those arranged at the initial and final stages is smaller than that of gate electrodes of the FETs arranged at the initial and final stages.

5. The switch as claimed in claim 1, further comprising a linkup interconnection line connected to the source or drain electrode of one of the at least three FETs arranged at the intermediate stage is shorter than that of other linkup interconnection line connected to the source or drain electrode of the FET at the initial or final stage.