Automated system for designing and developing field programmable gate arrays
DCFirst Claim
1. A system for programming a field programmable gate array (FPGA) comprising:
- means for analyzing a user-defined algorithm specified in a source code of a high level language and designed to process data vectors with at least one dimension;
means for identifying the vector processing operations of the source code;
means for mapping the vector processing operations onto logic components of an FPGA; and
means for programming the FPGA with the user-defined algorithm based on the mapping of the logic components.
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Litigations
1 Petition
Accused Products
Abstract
An automated system and method for programming field programmable gate arrays (FPGAS) is disclosed for implementing user-defined algorithms specified in a high level language. The system is particularly suited for use with image processing algorithms and can speed up the process of implementing and testing a fully written high-level user-defined algorithm to a matter of a few minutes, rather than the days, weeks or even months presently required using conventional software tools. The automated system includes an analyzer module and a mapper module. The analyzer determines what logic components are required and their interrelationships, and observes the relative timing between the required components and their partial products. The mapper module utilizes the output from the analyzer module and determines where the required logic components must be placed on a given target FPGA in order to reliably route, without interference, the required interconnections between various components and I/O.
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Citations
10 Claims
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1. A system for programming a field programmable gate array (FPGA) comprising:
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means for analyzing a user-defined algorithm specified in a source code of a high level language and designed to process data vectors with at least one dimension; means for identifying the vector processing operations of the source code; means for mapping the vector processing operations onto logic components of an FPGA; and means for programming the FPGA with the user-defined algorithm based on the mapping of the logic components. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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Specification