Static timing analysis and dynamic simulation for custom and ASIC designs

• US 7,590,953 B2
• Filed: 02/03/2006
• Issued: 09/15/2009
• Est. Priority Date: 02/03/2005
• Status: Active Grant

• Current Assignee: Sage Software Incorporated (Sage Group PLC)
• Original Assignee: Sage Software Incorporated (Sage Group PLC)
• Inventors: Chang, Mau-Chung
• Primary Examiner(s): Lin; Sun J
• Application Number:
  US11/347,029
• Publication Number:
  US 20060200786A1
• Time in Patent Office: 1,320 Days
• Field of Search: 716/6, 716/5, 716/4
• US Class Current: 716/113
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/3312 Timing analysis
• CPC Class Codes: G06F 30/3315 using static timing analysis [STA]
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Abstract

A single verification tool provides both static timing analysis and timing simulation capabilities targeted at both full-custom and ASIC designs in a unified environment. In various embodiments the verification tool includes the following features: (a) Integrating both static timing analysis and dynamic simulation tools into a single tool, (b) Efficient path search for multi-phase, multi-frequency and multi-cycle circuit in the presence of level sensitive latch, (c) Automatically identifying circuit structure, e.g. complex gate, for timing characterization, (d) Circuit structures at transistor level solved by incorporating function check, (e) Carrying out functional check to filter out failing path and identifying gate with simultaneously changing inputs, (f) Finding maximum operation frequency in the presence of level sensitive latches after filtering out false paths, (g) Crosstalk solver by utilizing the admittance matrix and voltage transfer of RLC part in frequency domain coupled with the non-linear driver in time domain implemented in spice-like simulator, (h) Making use of the correlation between inputs of aggressors and victim to determine switching time at victim'"'"'s output iteratively.

Claims

1. A method for verifying timing of a circuit using a single tool, the circuit having a first portion with a gate-level description and a second portion with a transistor-level description, comprising:

accepting both the gate-level and transistor-level descriptions; and

using the single tool to perform timing analysis of the circuit using both the gate-level and transistor-level descriptions,

wherein the step of using the single tool includes decomposing circuit structures into transistor-level descriptions to determine timing information associated with the transistor-level descriptions.

2. The method according to claim 1, wherein the step of using a single tool includes obtaining timing information associated with the gate-level descriptions from a pre-characterized timing library.

3. The method according to claim 1, wherein the decomposing step includes:

identifying unique circuit structures associated with certain of the transistor-level descriptions; and

performing function check to obtain the associated timing information.

4. The method according to claim 1, further comprising:

using the single tool to perform timing simulation of the circuit using both the gate-level and transistor-level descriptions.

5. The method according to claim 1, wherein the accepting step includes reading the gate-level and transistor-level descriptions from a SPICE netlist.

6. A method for verifying timing of a circuit using a single tool, comprising:

accepting descriptions of the circuit;

obtaining timing information associated with the descriptions; and

using the single tool to perform both timing analysis and timing simulation of the circuit using the descriptions and timing information, wherein the single tool includes a delay calculator that is capable of performing timing analysis of individual logic structures within the circuit, as well as performing timing simulation of the circuit as a whole.

7. The method according to claim 6, wherein the step of using a single tool includes partitioning the circuit based on the descriptions.

8. The method according to claim 6, wherein the descriptions include both gate-level and transistor-level descriptions.