Method for fabricating an integrated gate dielectric layer for field effect transistors
First Claim
1. A method for forming dielectric layers on a substrate, comprising:
- forming a silicon oxide layer on a substrate;
plasma treating nitrogen atoms into the silicon oxide layer using RF power applied at a duty cycle selected to provide a nitrogen concentration in the silicon oxide layer of between about 0.2E15 atoms/cm2 to about 1E15 atoms/cm2, wherein plasma treating the silicon oxide layer further comprises creating nucleation sites on the silicon oxide layer;
depositing a silicon nitride layer on the silicon oxide layer by an ALD process; and
thermal annealing the substrate.
1 Assignment
0 Petitions
Accused Products
Abstract
Methods for forming a integrated gate dielectric layer on a substrate are provided. In one embodiment, the method includes forming a silicon oxide layer on a substrate, plasma treating the silicon oxide layer, depositing a silicon nitride layer on the silicon oxide layer by an ALD process, and thermal annealing the substrate. In another embodiment, the method includes precleaning a substrate, forming a silicon oxide layer on the substrate, plasma treating the silicon oxide layer, depositing a silicon nitride layer on the silicon oxide layer by an ALD process, and thermal annealing the substrate, wherein the formed silicon oxide layer and the silicon nitride layer has a total thickness less than 30 Å utilized as a gate dielectric layer in a gate structure.
200 Citations
18 Claims
-
1. A method for forming dielectric layers on a substrate, comprising:
-
forming a silicon oxide layer on a substrate; plasma treating nitrogen atoms into the silicon oxide layer using RF power applied at a duty cycle selected to provide a nitrogen concentration in the silicon oxide layer of between about 0.2E15 atoms/cm2 to about 1E15 atoms/cm2, wherein plasma treating the silicon oxide layer further comprises creating nucleation sites on the silicon oxide layer; depositing a silicon nitride layer on the silicon oxide layer by an ALD process; and thermal annealing the substrate. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
-
-
14. A method for forming a gate dielectric layer on a substrate, comprising:
-
precleaning a substrate; forming a silicon oxide layer on the substrate; supplying a RF power between about 800 Watts and about 1400 Watts to form a plasma from a nitrogen containing gas, wherein the RF power is applied at a duty cycle selected to provide a nitrogen concentration in the silicon oxide layer of between about 0.2E15 atoms/cm2 to about 1E15 atoms/cm2, wherein the duty cycle includes at least one of pulsing the RF power or supplying power at a duty cycle of about 2 percent and about 50 percent; plasma treating the silicon oxide layer in the presence of the plasma formed from the nitrogen containing gas to obtain a nitrogen concentration in the silicon oxide layer between about 0.2E15 atoms/cm2 to about 1E15 atoms/cm2, wherein plasma treating the silicon oxide layer further comprises creating nucleation sites on the silicon oxide layer; depositing a silicon nitride layer on the silicon oxide layer by an ALD process; and thermal annealing the substrate, wherein the silicon oxide layer and the silicon nitride layer form a gate dielectric layer. - View Dependent Claims (15)
-
-
16. A method for forming a gate structure, comprising:
-
precleaning a substrate; forming a silicon oxide layer on the substrate; plasma treating nitrogen atoms into the silicon oxide layer using RF power applied at a duty cycle selected to provide a nitrogen concentration in the silicon oxide layer of between about 0.2E15 atoms/cm2 to about 1E15 atoms/cm2, wherein plasma treating the silicon oxide layer further comprises creating nucleation sites on the silicon oxide layer; depositing a silicon nitride layer on the silicon oxide layer by an ALD process; thermal annealing the substrate, wherein the silicon oxide layer and the silicon nitride layer has a total thickness less than 30 Å and
forms a gate dielectric;forming a gate electrode on the gate dielectric; and forming source and drain regions in the substrate proximate the gate electrode. - View Dependent Claims (17, 18)
-
Specification