Digital synthesizer for low power location receivers
First Claim
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1. A radio frequency (RF) phase locked loop (PLL) synthesizer, comprising:
- a variable oscillator (VCO) that generates a clock signal;
a fractional-N divider that has an fractional-N divider output coupled to a delta sigma modulator and in receipt of the clock signal;
an integer divider that has an integer divider output in receipt of the clock signal; and
a phase frequency detector (PFD) in receipt of either the fractional-N divider output or the integer divider output that is selected with a bypass signal, where the fractional-N divider, integer divider and PFD are formed in a CMOS logic block.
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Abstract
A high-frequency phase locked loop synthesizer having a selectable fractional-N divider and integer divider along with a phase frequency detector implemented as a CMOS logic block.
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Citations
24 Claims
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1. A radio frequency (RF) phase locked loop (PLL) synthesizer, comprising:
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a variable oscillator (VCO) that generates a clock signal; a fractional-N divider that has an fractional-N divider output coupled to a delta sigma modulator and in receipt of the clock signal; an integer divider that has an integer divider output in receipt of the clock signal; and a phase frequency detector (PFD) in receipt of either the fractional-N divider output or the integer divider output that is selected with a bypass signal, where the fractional-N divider, integer divider and PFD are formed in a CMOS logic block. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A method for radio frequency (RF) phase looked loop (PLL) synthesizing, comprising:
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generating a clock signal with a variable oscillator (VCO); dividing the clock signal with a fractional-N divider that has an fractional-N divider output coupled to a delta sigma modulator and in receipt of the clock signal; dividing the clock signal with an integer divider that has an integer divider output in receipt of the clock signal; and selecting either the fractional-N divider output or the integer divider output with a bypass signal to be processed by a phase frequency detector (PFD), where the selecting occurs in a CMOS logic block. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24)
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Specification