Selective scrambler for use in a communication system and method to minimize bit error at the receiver
First Claim
1. A circuit for transmitting a sequence of bits, comprising:
- a memory;
an output circuit coupled to the memory for scrambling a payload section of a frame that includes the payload section, a preamble section, and a parity section, wherein said scrambling comprises inverting a logic value of at least one of the sequence of bits within the payload section;
an enable circuit coupled to the memory for;
(i) enabling the memory to receive the sequence of bits within the payload section of the frame, and (ii) disabling the memory during times in which the transmitting circuit is presented with the preamble and parity sections of the frame; and
a state machine coupled to the enable circuit for detecting the times during which the transmitting circuit is presented with the preamble and parity sections of the frame.
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Accused Products
Abstract
A communication system for transmitting and receiving a sequence of bits, and the methodology for transferring that sequence of bits are provided. The communication system includes a transmitting circuit and a receiving circuit. Within the transmitting circuit is a scrambler that comprises a shift register, an enable circuit, and an output circuit. The shift register temporarily stores n bits within the sequence of bits, and the enable circuit enables the shift register to store bits that arise only within the payload section of a frame. The output circuit includes a feedback, and several taps within the n stages to scramble logic values within the sequence of n bits output from the shift registers thus effectively preventing in most instances the sequence of bits from exceeding n number of the same logic value. Within the receiving circuit is a descrambler also having a shift register, an enable circuit, and an output circuit. The descrambler recompiles the scrambled data back to its original form. The scrambler is preferably placed before an encoder in the transmission path to minimize data dependent, low frequency jitter. The encoder is used to place a coding violation into the frame to signal the beginning of each frame, and to encode the parity with an offset against any DC accumulation of the coding violation and the scrambled payload to eliminate all DC accumulation (baseline wander) within each frame.
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Citations
20 Claims
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1. A circuit for transmitting a sequence of bits, comprising:
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a memory; an output circuit coupled to the memory for scrambling a payload section of a frame that includes the payload section, a preamble section, and a parity section, wherein said scrambling comprises inverting a logic value of at least one of the sequence of bits within the payload section; an enable circuit coupled to the memory for;
(i) enabling the memory to receive the sequence of bits within the payload section of the frame, and (ii) disabling the memory during times in which the transmitting circuit is presented with the preamble and parity sections of the frame; anda state machine coupled to the enable circuit for detecting the times during which the transmitting circuit is presented with the preamble and parity sections of the frame. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A communication system, comprising:
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a scrambler coupled to temporarily store n bits of a sequence of bits within a payload section of a frame that includes the payload section, a preamble section, and a parity section, where said scrambler inverts a logic value of a first bit within the sequence if a logic value of a next consecutive bit within the sequence and a logic value of a nth bit within the sequence are dissimilar; an encoder coupled to an output of the scrambler for coding the n bits; an enable circuit coupled to the scrambler for;
(i) enabling a memory within the scrambler to receive the n bits within the payload section of the frame, and (ii) disabling the memory during times in which the communication system is presented with the preamble and parity sections of the frame;a state machine coupled to the enable circuit for detecting the times during which the communication system is presented with the preamble and parity sections of the frame; a transmission path coupled to an output of the encoder for receiving the coded n bits; a decoder coupled to the transmission path for decoding the coded n bits; and a descrambler coupled to temporarily store the decoded n bits as a sequence of decoded bits and invert a logic value of a first bit within the sequence of decoded bits if a logic value of a next consecutive bit and a logic value of an nth bit within the sequence of decoded bits are dissimilar. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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Specification