Selective scrambler for use in a communication system and method to minimize bit error at the receiver

• US 20060083328A1
• Filed: 10/15/2004
• Published: 04/20/2006
• Est. Priority Date: 10/15/2004
• Status: Active Grant

• Current Assignee: Microchip Technology Incorporated
• Original Assignee: Standard Microsystems Corporation (Microchip Technology Incorporated)
• Inventors: Ho, Horace C., Knapp, David J., Green, Christopher M.
• Granted Patent: US 7,634,694 B2
• Time in Patent Office: Days
• US Class Current: 375/295
• CPC Class Codes: H04L 1/0061 Error detection codes
• CPC Class Codes: H04L 25/03866 using scrambling

Abstract

A communication system for transmitting and receiving a sequence of bits, and the methodology for transferring that sequence of bits are provided. The communication system includes a transmitting circuit and a receiving circuit. Within the transmitting circuit is a scrambler that comprises a shift register, an enable circuit, and an output circuit. The shift register temporarily stores n bits within the sequence of bits, and the enable circuit enables the shift register to store bits that arise only within the payload section of a frame. The output circuit includes a feedback, and several taps within the n stages to scramble logic values within the sequence of n bits output from the shift registers thus effectively preventing in most instances the sequence of bits from exceeding n number of the same logic value. Within the receiving circuit is a descrambler also having a shift register, an enable circuit, and an output circuit. The descrambler recompiles the scrambled data back to its original form. The scrambler is preferably placed before an encoder in the transmission path to minimize data dependent, low frequency jitter. The encoder is used to place a coding violation into the frame to signal the beginning of each frame, and to encode the parity with an offset against any DC accumulation of the coding violation and the scrambled payload to eliminate all DC accumulation (baseline wander) within each frame.

Claims

1. A circuit for transmitting a sequence of bits, comprising:

a memory;

an enable circuit coupled to the memory for enabling the memory to receive the sequence of bits; and

an output circuit coupled to the memory for inverting a logic value of at least one of the sequence of bits within a payload section of a frame that includes a payload section and a preamble section.

2. The transmitting circuit of claim 1, wherein the memory comprises a shift register.

3. The transmitting circuit of claim 1, wherein the output circuit is coupled to receive the at least one of the sequence of bits from the memory, invert the at least one logic value, and forward the inverted said at least one logic value back to the memory.

4. The transmitting circuit of claim 1, wherein the memory comprises:

n number of flip flops coupled in series;

wherein an input of the first flip flop in the series is coupled to an output of the output circuit; and

wherein an output of the nth flip flop and the n−

1 flip flop in the series is coupled to a pair of inputs of the output circuit.

5. The transmitting circuit of claim 1, wherein the enable circuit and the output circuit each comprise combinatorial logic.

6. The transmitting circuit of claim 1, wherein the frame further comprises a parity section.

7. The transmitting circuit of claim 6, wherein the enable circuit comprises:

a pair of inputs; and

an output coupled to disable outputs from the memory if the pair of inputs receive a signal indicating the preamble section or the parity section are presented to the transmitting circuit.

8. The transmitting circuit of claim 1, wherein the inverted logic value is that of a first bit within the sequence if the logic values of a second bit within the sequence and an nth bit within the sequence are dissimilar.

9. The transmitting circuit of claim 1, wherein the output circuit is further coupled for not inverting the logic value of a first bit within the sequence if the logic values of a second bit within the sequence and an nth bit within the sequence are the same.

10. The transmitting circuit of claim 1, wherein the memory comprises n stages for storing each of the sequence of n bits, and the output circuit comprises:

three inputs coupled to receive the first bit from the nth stage of the n stages, the second bit from the n−

1 stage of the n stages, and the nth bit; and

an output coupled to place upon an input of the first stage of the n stages the inverted logic value.

11. The transmitting circuit of claim 1, further comprising an encoder coupled between the output circuit and a transmission path for coding the inverted logic value and placing the coded inverted logic value upon the transmission path.

12. The transmitting circuit of claim 1, further comprising an encoder for encoding the preamble section with a coding violation.

13. The transmitting circuit of claim 1, further comprising an encoder for encoding a parity section arranged in a different region within the frame than the payload section and the preamble section, and wherein the parity section is encoded with logic values that when combined with an encoded preamble section and an encoded payload section present substantially no DC accumulation within a single said frame when received upon a receiver.

14. The transmitting circuit of claim 1, wherein the output circuit prevents the sequence of bits output from the shift register from exceeding n number of the same logic value.

15. A communication system, comprising:

a scrambler coupled to temporarily store n bits of a sequence of bits and to invert a logic value of a first bit within the sequence if a logic value of a second bit within the sequence and a logic value of a nth bit within the sequence are dissimilar;

an encoder coupled to an output of the scrambler for coding the n bits;

a transmission path coupled to an output of the encoder for receiving the coded n bits;

a decoder coupled to the transmission path for decoding the coded n bits; and

a descrambler coupled to temporarily store the decoded n bits as a sequence of decoded bits and invert a logic value of the first bit within the sequence of decoded bits if the logic values of the second bit and a logic value of the nth bit within the sequence of decoded bits are dissimilar.

16. The communication system as recited of claim 15, wherein the scrambler is coupled to temporarily store the n bits within only a payload section of a frame that comprises the payload section, a preamble section and a parity section.

17. The communication system as recited of claim 15, wherein logic one voltage values of the coded n bits transition at twice the frequency as logic zero voltage values.

18. The communication system as recited of claim 15, wherein the coded n bits incur a transition near the beginning of an m clock cycle provided a logic one voltage value occurs during the m+1 clock cycle and the sum of DC voltage values of all coded logic one and logic zero voltages values is skewed toward either the one or logic low voltage value prior to the m clock cycle.

19. The communication system as recited of claim 15, wherein the transmission path is an optical medium.

20. The communication system as recited of claim 15, wherein the encoder is coupled to code an additional m bits within a preamble section of a frame that precedes the n bits within a payload section of the frame, and for coding the m bits with a sequence that is recognizable by the decoder as a coding violation to synchronize the beginning of the frame as well as the payload section within the frame.

21. The communication system as recited of claim 15, wherein the encoder is coupled to code an additional p bits within a parity section of a frame that is subsequent to the n bits within the payload section, and for coding the p bits with a sequence that maintains parity with the n bits within the payload section.

22. A method for transferring a sequence of bits, comprising:

substituting a substantially random set of logic values among n bits of the sequence of bits to decrease a jitter period;

changing the transition period of the substantially random set of logic values to decrease DC accumulation; and

transferring the substantially random set of logic values with changed transition period across a transmission medium.

23. The method as recited in claim 22, wherein said substituting comprises:

temporarily storing n bits of the sequence of bits; and

inverting the logic value of a first bit within the sequence if the logic values of a second bit within the sequence and a nth bit within the sequence are dissimilar.

24. The method as recited in claim 22, wherein said substituting comprises:

temporarily storing n bits of the sequence of bits; and

maintaining the logic value of a first bit within the sequence if the logic values of a second bit within the sequence and a nth bit within the sequence are similar.

25. The method as recited in claim 22, wherein said changing comprises transitioning logic one voltage values at twice the rate as logic zero voltage values.

26. The method as recited in claim 22, wherein said changing comprises:

computing a sum of DC voltage values for logic zero and logic one voltage values prior to an m cycle;

detecting a logic one voltage value with the n bits during the m clock cycle and the m+1 clock cycle; and

producing a transition near the beginning of the m clock cycle provided the computed sum of the DC voltage values is skewed toward either the logic one or logic zero voltage values.

27. The method as recited in claim 22, wherein said substituting occurs on n bits within only a payload section of a frame, and wherein said changing the transition period occur on n bits within the payload section and m bits within a preamble section preceding the payload section and on p bits within a parity section subsequent to the payload section.

28. The method as recited in claim 22, further comprising:

subsequent to said transferring, changing back the transition period of the substantially random set of logic values that have the changed transition period; and

substituting the sequence of bits among the substantially random set of logic values among n bits of the sequence of bits.