Structure and method for forming laterally extending dielectric layer in a trench-gate FET

• US 7,648,877 B2
• Filed: 06/24/2005
• Issued: 01/19/2010
• Est. Priority Date: 06/24/2005
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Andrews, John Tracey
• Primary Examiner(s): Coleman; W. David
• Assistant Examiner(s): MCCALL SHEPARD, SONYA D
• Application Number:
  US11/166,356
• Publication Number:
  US 20060289929A1
• Time in Patent Office: 1,670 Days
• Field of Search: 438/586, 438/268, 438/270
• US Class Current: 438/270
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A field effect transistor (FET) is formed as follows. A trench is formed in a silicon region. An oxidation barrier layer is formed over a surface of the silicon region adjacent the trench and along the trench sidewalls and bottom. A protective layer is formed over the oxidation barrier layer inside and outside the trench. The protective layer is partially removed such that a portion of the oxidation barrier layer extending at least along the trench bottom becomes exposed and portions of the oxidation barrier layer extending over the surface of the silicon region adjacent the trench remain covered by remaining portions of the protective layer.

Claims

1. A method of forming a FET, comprising:

forming a trench in a silicon region;

forming a silicon nitride layer over a surface of the silicon region adjacent the trench and along the trench sidewalls and bottom;

forming an oxide layer over the silicon nitride layer such that the oxide layer is thicker along the surface of the silicon region adjacent the trench than along the trench bottom;

uniformly etching back the oxide layer such that a portion of the silicon nitride layer extending along the trench bottom and along at least a portion of the trench sidewalls becomes exposed while portions of the silicon nitride layer extending over the surface of the silicon region adjacent the trench remain covered by remaining portions of the oxide layer;

removing the exposed portion of the silicon nitride layer along the trench bottom using an anisotropic etch process;

removing the remaining portions of the oxide layer; and

thereafter

forming a dielectric layer along the trench bottom using a local oxidation of silicon (LOCOS) process.

2. A method of forming a FET, comprising:

forming a trench in a silicon region;

forming a silicon nitride layer over a surface of the silicon region adjacent the trench and along the trench sidewalls and bottom;

forming an oxide layer over the silicon nitride layer such that the oxide layer is thicker along the surface of the silicon region adjacent the trench than along the trench bottom;

uniformly etching back the oxide layer such that a portion of the silicon nitride layer extending along the trench bottom and along at least a portion of the trench sidewalls becomes exposed while portions of the silicon nitride layer extending over the surface of the silicon region adjacent the trench remain covered by remaining portions of the oxide layer;

removing the exposed portion of the silicon nitride layer along the trench bottom using an anisotropic etch process;

removing the remaining portions of the oxide layer;

thereafter

forming a dielectric layer along the trench bottom using a local oxidation of silicon (LOCOS) process;

removing remaining portions of the nitride layer;

forming a gate oxide along trench sidewalls; and

forming a recessed gate electrode over the gate oxide in the trench.

3. A method of forming a FET, comprising:

forming a trench in a semiconductor region;

forming an oxidation barrier layer directly over a surface of the semiconductor region adjacent the trench and along the trench sidewalls and bottom;

forming a protective layer directly over the oxidation barrier layer inside and outside the trench;

partially removing the protective layer such that a portion of the oxidation barrier layer extending at least along the trench bottom becomes exposed and portions of the oxidation barrier layer extending over the surface of the semiconductor region adjacent the trench remain covered by remaining portions of the protective layer;

removing the exposed portion of the oxidation barrier layer from along the trench bottom;

removing the remaining portions of the protective layer; and

thereafter

forming a dielectric layer along the bottom of the trench.

4. A method of forming a FET, comprising:

forming a trench in a semiconductor region;

forming an oxidation barrier layer directly over a surface of the semiconductor region adjacent the trench and along the trench sidewalls and bottom;

forming a protective layer directly over the oxidation barrier layer inside and outside the trench;

partially removing the protective layer such that a portion of the oxidation barrier layer extending at least along the trench bottom becomes exposed and portions of the oxidation barrier layer extending over the surface of the semiconductor region adjacent the trench remain covered by remaining portions of the protective layer;

removing the exposed portion of the oxidation barrier layer from along the trench bottom;

thereafter

forming a dielectric layer along the bottom of the trench;

removing remaining portions of the oxidation barrier layer;

forming a gate oxide along the trench sidewalls; and

forming a recessed gate electrode over the dielectric layer in the trench.