ISI reduction technique
First Claim
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1. A switch capacitor circuit comprising:
- a voltage source having a first terminal and a second terminal;
a first capacitor;
a second capacitor;
a third capacitor;
a fourth capacitor;
a first pair of switches configured to couple the first capacitor in parallel to the second capacitor, wherein one switch of the first pair of switches is configured to couple the second capacitor to the first terminal of the voltage source;
a second pair of switches configured to couple the third capacitor in parallel to the fourth capacitor, wherein one switch of the second pair of switches is configured to couple the third capacitor to the second terminal of the voltage source;
a third pair of switches configured to couple the first capacitor in parallel to the third capacitor, wherein one switch of the third pair of switches is configured to couple the third capacitor to the first terminal of the voltage source; and
a fourth pair of switches configured to couple the second capacitor in parallel to the fourth capacitor, wherein one switch of the fourth pair of switches is configured to couple the second capacitor to the second terminal of the voltage source.
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Abstract
The invention refers to signal processing circuits, more particularly, to switch capacitor circuits, and methods for reducing inter-symbol-interference. A switch capacitor circuit with reduced Inter-Symbol-Interference effect is provided, comprising: a voltage source, a first capacitor, a second capacitor, and at least one switch configured to be switched in a way that the first capacitor is charged to a first voltage by means of the voltage source, and then discharged by means of the second capacitor, thereby reducing the Inter-Symbol-Interference effect.
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Citations
10 Claims
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1. A switch capacitor circuit comprising:
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a voltage source having a first terminal and a second terminal; a first capacitor; a second capacitor; a third capacitor; a fourth capacitor; a first pair of switches configured to couple the first capacitor in parallel to the second capacitor, wherein one switch of the first pair of switches is configured to couple the second capacitor to the first terminal of the voltage source; a second pair of switches configured to couple the third capacitor in parallel to the fourth capacitor, wherein one switch of the second pair of switches is configured to couple the third capacitor to the second terminal of the voltage source; a third pair of switches configured to couple the first capacitor in parallel to the third capacitor, wherein one switch of the third pair of switches is configured to couple the third capacitor to the first terminal of the voltage source; and a fourth pair of switches configured to couple the second capacitor in parallel to the fourth capacitor, wherein one switch of the fourth pair of switches is configured to couple the second capacitor to the second terminal of the voltage source. - View Dependent Claims (2, 3, 4)
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5. A method for reducing an Inter-Symbol-Interference effect, comprising:
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charging a first capacitor and a second capacitor to a first voltage with at least one voltage source; charging a third capacitor and a fourth capacitor to a second voltage with the at least one voltage source, wherein the second voltage has substantially the same absolute value as the first voltage, but is opposite in sign; discharging the first capacitor through the fourth capacitor, comprising decoupling the first capacitor from the second capacitor and coupling the first capacitor in parallel to the fourth capacitor; and discharging the third capacitor through the second capacitor, comprising decoupling the third capacitor from the fourth capacitor and coupling the third capacitor in parallel to the second capacitor. - View Dependent Claims (6, 7, 8)
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9. An apparatus, comprising:
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a voltage source having a first terminal and a second terminal; a first capacitor having a first terminal; a second capacitor having a first terminal; a third capacitor having a first terminal; a fourth capacitor having a first terminal; a first switch having a first terminal coupled to the first terminal of the voltage source and a second terminal coupled to the first terminal of the first capacitor; a second switch having a first terminal coupled to the second terminal of the first switch and a second terminal coupled to the first terminal of the second capacitor; a third switch having a first terminal coupled to the first terminal of the third capacitor and a second terminal coupled to the first terminal of the fourth capacitor; a fourth switch having a first terminal coupled to the second terminal of the first switch and a second terminal coupled to the second terminal of the third switch; and a fifth switch having a first terminal coupled to the second terminal of the first switch and a second terminal coupled to the first terminal of the third switch. - View Dependent Claims (10)
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Specification