Method for packaging circuits and packaged circuits

• US 7,712,211 B2
• Filed: 12/23/2003
• Issued: 05/11/2010
• Est. Priority Date: 05/06/2003
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Boon, Suan Jeung, Chua, Swee Kwang, Chia, Yong Poo, Koon, Eng Meow, Waf, Low Siu
• Primary Examiner(s): CHANG, RICK KILTAE
• Application Number:
  US10/744,632
• Publication Number:
  US 20040221451A1
• Time in Patent Office: 2,331 Days
• Field of Search: 298/32, 298/40, 298/41, 174/521, 174/527, 174/528, 174/534, 361/728, 361/772, 361/783, 361/820
• US Class Current: 29/841
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 22/00 Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06548 Conductive via connections through the substrate, container, or encapsulation
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/06558 the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
• CPC Class Codes: H01L 2225/06575 Auxiliary carrier between devices, the carrier having no electrical connection structure
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: Y10T 29/49128 : Assembling formed circuit to base
• CPC Class Codes: Y10T 29/4913 : Assembling to base an electrical component, e.g., capacitor, etc.
• CPC Class Codes: Y10T 29/49144 : by metal fusion
• CPC Class Codes: Y10T 29/49146 : with encapsulating, e.g., potting, etc.
• CPC Class Codes: Y10T 29/49155 : Manufacturing circuit on or in base
• CPC Class Codes: Y10T 29/49165 : by forming conductive walled aperture in base
• CPC Class Codes: Y10T 29/49167 : with deforming of conductive path
• CPC Class Codes: Y10T 29/49169 : Assembling electrical component directly to terminal or elongated conductor
• CPC Class Codes: Y10T 29/49794 : Dividing on common outline

Abstract

A method for packaging integrated circuit chips (die) is described that includes providing a base substrate with package level contacts, coating a base substrate with adhesive, placing dies on the adhesive, electrically connecting the die to the package level contacts, and removing the backside of the base substrate to expose the backside of the package level contacts. Accordingly, an essentially true chip scale package is formed. Multi-chip modules are formed by filling gaps between the chips with an encapsulant. In an embodiment, chips are interconnected by electrical connections between package level contacts in the base substrate. In an embodiment, substrates each having chips are adhered back-to-back with through vias formed in aligned saw streets to interconnect the back-to-back chip assembly.

Claims

1. A method, comprising:

providing a die;

providing a substrate having electrical signal terminals thereon;

fixing the die on the substrate;

forming electrical connections from die to the terminals; and

removing a backside of substrate to expose the terminals, wherein removing includes removing a portion of a semiconductor from the backside of the substrate.

2. The method of claim 1, wherein providing a die includes providing a die including an integrated circuit memory device.

3. The method of claim 1, wherein fixing the die on the substrate includes applying adhesive to a top surface of the substrate, placing the die on the adhesive, and curing the adhesive to fix the die on the substrate top surface.

4. The method of claim 1, wherein providing the die includes providing a die having I/O pads on a top surface of the die.

5. A method, comprising:

forming active devices on a first substrate;

singulating the active devices;

forming electrical terminals on a second semiconductor substrate;

coating the second substrate with an adhesive;

placing a plurality of active devices on the adhesive;

curing the adhesive;

electrically connecting the active devices to respective electrical terminals;

removing a backside of the second substrate to expose a backside of the electrical terminals; and

singulating the second substrate to form individual chip scale packages that include at least one active device and a portion of the second substrate.

6. The method of claim 5, wherein forming electrical terminals includes patterning a conductive layer on a top surface of the second substrate.

7. The method of claim 6, wherein patterning the conductive layer includes patterning a metal layer.

8. The method of claim 6, wherein forming electrical terminals includes planarizing the top surface of the second substrate.

9. The method of claim 6, wherein removing a backside of the second substrate includes backgrinding the second substrate.

10. The method of claim 9, wherein electrically connecting the active devices to respective electrical terminals includes routing a metal trace from a bond pad on top of the active device to the electrical terminal below the active device.

11. The method of claim 10, wherein routing the metal trace includes routing the metal trace to an electrical terminal at least partially beneath the active device.

12. The method of claim 5, wherein electrically connecting the active devices to respective electrical terminals includes filling gaps between the active devices with a non-conductive material.

13. The method of claim 12, wherein singulating the second substrate includes cutting through non-conductive material in the gaps between the active devices.

14. A method, comprising:

providing a semiconductor substrate having electrical signal terminals thereon;

placing adhesive on a top surface of the substrate;

placing a die having top surface bond pads on adhesive to fix the die to the substrate;

forming electrical connections from top surface bond pads to the substrate terminals; and

removing a backside of substrate to expose terminals, wherein removing includes removing a portion of a semiconductor from the backside of the substrate.

15. The method of claim 14, wherein removing the backside of the substrate includes backgrinding the substrate.

16. The method of claim 14, wherein removing the backside of the substrate includes etching the back surface of the substrate.

17. The method of claim 14, wherein forming electrical connections includes removing adhesive not covered by the die from the top surface of the substrate and forming a trace from the top surface bond pads along the sides of the die to contact the substrate electrical signal terminal.

18. The method of claim 17, wherein forming the trace includes using metal redistribution to join the top surface bond pad and the substrate electrical signal terminal.

19. A method, comprising:

fixing a plurality of dice on a semiconductor substrate over a plurality of package terminals such that adjacent die overlie common package terminals;

electrically connecting I/O pads of the dice to the plurality of package terminals;

removing a backside of the substrate to expose the plurality of package terminals; and

singulating the plurality of dice with a portion of the substrate directly beneath each die to form a chip scale package.

20. The method of claim 19, wherein singulating includes cutting through the common package terminals such that a first portion remains with a first of the plurality of dice and a second portion remains with a second of the plurality of die.

21. A method, comprising:

providing a sensor die having a sensing device and an I/O pad at a top surface;

providing a semiconductor substrate having electrical signal terminals thereon;

fixing the die on the substrate;

forming electrical connections from the I/O pad of the die to the substrate terminals; and

removing a backside of substrate to expose the terminals.

22. The method of claim 21, wherein providing the sensor die includes providing a sensor die with an optical sensor in electrical communication with the I/O pad.

23. The method of claim 21, wherein fixing the die includes applying adhesive over the substrate, and curing the adhesive.

24. The method of claim 21, wherein forming electrical connections includes forming an aperture through an adhesive interposed between the die and the substrate to expose the electrical signal terminals, and forming a conductive trace from the I/O pad down the side of the die to the electrical signal terminal of the substrate.

25. The method of claim 24, wherein removing the backside of the substrate includes singulating the die from the remainder of the substrate.