Microelectronic assemblies having compliancy and methods therefor
First Claim
1. A method of making a microelectronic assembly comprising:
- providing a microelectronic element having a first surface and contacts accessible at the first surface;
providing compliant dielectric bumps over the first surface of said microelectronic element;
depositing a sacrificial layer over said compliant dielectric bumps and the first surface of said microelectronic element, wherein said sacrificial layer covers said compliant dielectric bumps;
grinding said sacrificial layer and said compliant dielectric bumps so as to planarize top surfaces of said compliant dielectric bumps, wherein the planarized top surfaces of said compliant dielectric bumps are exposed;
after the grinding step, removing at least portions of said sacrificial layer to expose at least some of said contacts; and
forming conductive traces having first ends electrically connected with said contacts and second ends overlying the planarized top surfaces of said compliant dielectric bumps.
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Accused Products
Abstract
A method of making a microelectronic assembly includes providing a semiconductor wafer having contacts accessible at a first surface, forming compliant bumps over the first surface and depositing a sacrificial layer over the compliant bumps. The method includes grinding the sacrificial layer and the compliant bumps so as to planarize top surfaces of the compliant bumps, whereby the planarized top surfaces are accessible through said sacrificial layer. The sacrificial layer is removed to expose the compliant bumps and the contacts. A silicone layer is deposited over the compliant bumps and portions of the silicone layer are removed to expose the contacts accessible at the first surface of the semiconductor wafer. Conductive traces are formed having first ends electrically connected with the contacts and second ends overlying the compliant bumps and conductive elements are provided atop the second ends of the traces.
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Citations
34 Claims
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1. A method of making a microelectronic assembly comprising:
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providing a microelectronic element having a first surface and contacts accessible at the first surface; providing compliant dielectric bumps over the first surface of said microelectronic element; depositing a sacrificial layer over said compliant dielectric bumps and the first surface of said microelectronic element, wherein said sacrificial layer covers said compliant dielectric bumps; grinding said sacrificial layer and said compliant dielectric bumps so as to planarize top surfaces of said compliant dielectric bumps, wherein the planarized top surfaces of said compliant dielectric bumps are exposed; after the grinding step, removing at least portions of said sacrificial layer to expose at least some of said contacts; and forming conductive traces having first ends electrically connected with said contacts and second ends overlying the planarized top surfaces of said compliant dielectric bumps. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
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22. A method of making a microelectronic assembly comprising:
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providing a microelectronic element having a first surface and contacts accessible at the first surface; providing dielectric bumps over the first surface of said microelectronic element; depositing a sacrificial layer over said dielectric bumps; grinding said sacrificial layer and said dielectric bumps so as to planarize top surfaces of said dielectric bumps, wherein the planarized top surfaces are exposed; after the grinding step, removing at least portions of said sacrificial layer as to expose said dielectric bumps and said contacts; depositing a dielectric layer over the first surface of said microelectronic element and said dielectric bumps; selectively removing said dielectric layer so as to expose said contacts exposed at the first surface of said microelectronic element; forming conductive traces having first ends electrically connected with said contacts and second ends overlying the planarized top surfaces of said dielectric bumps; and providing conductive elements in contact with the second ends of said conductive traces. - View Dependent Claims (23, 24, 25, 26, 27, 28, 29, 30)
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31. A method of making a microelectronic assembly comprising:
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providing a semiconductor wafer having a first surface and contacts accessible at the first surface; forming compliant dielectric bumps over the first surface of said semiconductor wafer; depositing a sacrificial layer over said compliant dielectric bumps; grinding said sacrificial layer and said compliant dielectric bumps so as to planarize top surfaces of said compliant dielectric bumps, wherein the planarized top surfaces of said compliant dielectric bumps are exposed; after the grinding step, removing remaining portions of said sacrificial layer so as to expose said compliant dielectric bumps and said contacts; depositing a silicone layer over the first surface of said microelectronic element and said compliant dielectric bumps; selectively removing said silicone layer so as to expose said contacts accessible at the first surface of said semiconductor wafer; forming conductive traces having first ends electrically connected with said contacts and second ends overlying the planarized top surfaces of said compliant dielectric bumps; and providing conductive elements in contact with the second ends of said conductive traces. - View Dependent Claims (32, 33, 34)
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Specification