Stackable semiconductor chip layer comprising prefabricated trench interconnect vias

• US 7,786,562 B2
• Filed: 06/10/2005
• Issued: 08/31/2010
• Est. Priority Date: 11/11/1997
• Status: Expired due to Fees

• Current Assignee: Nytell Software LLC (Intellectual Ventures LLC)
• Original Assignee: Aprolase Development Co LLC (Intellectual Ventures LLC)
• Inventors: Albert, Douglas, Pepe, Angel, Camien, Andrew, Boyd, W. Eric, Ozguz, Volkan, Yamaguchi, James
• Primary Examiner(s): CLARK, JASMINE JHIHAN B
• Application Number:
  US11/150,712
• Publication Number:
  US 20050277288A1
• Time in Patent Office: 1,908 Days
• Field of Search: 257/686, 257/777, 257/E25.006, 257/E25.013, 257/E25.018, 257/E25.021, 257/E25.027, 257/E23.085, 257/E21.614, 257/774, 257/723, 257/750, 438/109, 438/FOR.368, 438/FOR.426
• US Class Current: 257/686
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/02 Bonding areas; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/02372 connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13009 Bump connector integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16146 the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/02 Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 Technical content checked by a classifier
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01074 Tungsten [W]
• CPC Class Codes: H01L 2924/01082 Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance

Abstract

A stackable layer and stacked multilayer module are disclosed. Individual integrated circuit die are tested and processed at the wafer level to create vertical area interconnect vias for the routing of electrical signals from the active surface of the die to the inactive surface. Vias are formed at predefined locations on each die on the wafer at the reticle level using a series of semiconductor processing steps. The wafer is passivated and the vias are filled with a conductive material. The bond pads on the die are exposed and a metallization reroute from the user-selected bond pads and vias is applied. The wafer is then segmented to form thin, stackable layers that can be stacked and vertically electrically interconnected using the conductive vias, forming high-density electronic modules which may, in turn, be further stacked and interconnected to form larger more complex stacks.

Claims

1. An electronic module comprising:

a plurality of semiconductor chip layers, wherein at least one of the plurality of semiconductor chip layers includes a semiconductor substrate having a first surface and a second surface;

electronic circuitry comprising a plurality of circuit elements defined on the first surface during a predetermined series of semiconductor process steps using a predetermined reticle set;

a trench having an interior surface between at least one of the plurality of circuit elements and the second surface, wherein the trench is defined concurrently with the electronic circuitry during the predetermined series of semiconductor process steps using the predetermined reticle set;

a dielectric material located on the interior surface;

an electrically conductive material located on the dielectric material;

an electrically conductive via defined by removing a predetermined portion of the second surface to expose the electrically conductive material, wherein the plurality of semiconductor chip layers are stacked and bonded to form a module, and wherein the electrically conductive via electrically couples the electronic circuitry of the at least one of the plurality of semiconductor chip layers to the electronic circuitry of at least one other of the plurality of semiconductor chip layers in the electronic module; and

an element disposed between at least two of the plurality of semiconductor chip layers and configured to provide thermal management for at least one of the plurality of semiconductor chip layers.

2. The electronic module of claim 1, wherein the element configured to provide thermal management comprises a thermally-conductive adhesive.

3. The electronic module of claim 1, wherein the element configured to provide thermal management comprises a thermally-conductive epoxy.

4. The electronic module of claim 1, further comprising at least one T-connect.

5. The electronic module of claim 1, wherein at least two of the plurality of semiconductor chip layers are bonded together with a Z-conductive epoxy.

6. An electronic module comprising:

a plurality of semiconductor chip layers; and

an element located between two of the plurality of semiconductor chip layers and configured to provide thermal management for at least one of the plurality of semiconductor chip layers;

wherein at least one of the plurality of semiconductor chip layers includes;

a substrate comprising a first surface and a second surface;

electronic circuitry comprising a circuit element formed on the first surface;

a trench located in the first surface between the circuit element and the second surface of the substrate, wherein the trench has an interior surface;

a dielectric material on the interior surface of the trench; and

a conductive material located within the trench and configured to form an electrically conductive via between the first and second surfaces of the substrate, wherein the electrically conductive via is electrically connected to the electronic circuitry.

7. The electronic module of claim 6, wherein the element configured to provide thermal management comprises a thermally-conductive adhesive film.

8. The electronic module of claim 6, wherein the element configured to provide thermal management comprises a micro-heat pipe structure.

9. The electronic module of claim 6, wherein the element configured to provide thermal management comprises an interleaved-copper thermal-management layer.

10. The electronic module of claim 6, wherein the at least one of the plurality of semiconductor chip layers is backthinned.

11. The electronic module of claim 6, wherein the at least one of the plurality of semiconductor chip layers further comprises a bond pad electrically connected to and disposed between the electronic circuitry and the electrically conductive via.

12. The electronic module of claim 6, wherein the at least one of the plurality of semiconductor chip layers further comprises a passivation layer disposed over at least a portion of the at least one of the plurality of semiconductor chip layers.

13. The electronic module of claim 6, wherein the at least one of the plurality of semiconductor chip layers further comprises a conductive trace configured to electrically connect a bond pad to the electrically conductive via.

14. The electronic module of claim 13, wherein the bond pad is disposed on the first surface of the substrate at a distance from the electrically conductive via, and wherein the conductive trace extends along the first surface of the substrate between the bond pad and the electrically conductive via.

15. The electronic module of claim 6, wherein the at least one of the plurality of semiconductor chip layers further includes a conductive trace configured to electrically connect the electrically conductive via to a conductive T-connect structure at a lateral surface of the electronic module.

16. The electronic module of claim 6, wherein the conductive material comprises at least one of a doped polysilicon or a metal.

17. An electronic module comprising:

an element located between a first semiconductor chip layer and a second semiconductor chip layer and configured to provide thermal management for at least one of the first and second semiconductor chip layers, wherein the first and second semiconductor chip layers each include;

a substrate comprising a first surface and a second surface, wherein the first surface has electronic circuitry provided thereon;

a trench in the first surface between the electronic circuitry and the second surface, wherein the trench has an interior surface covered, at least in part, by a dielectric material; and

a conductive material disposed within the trench to form an electrically conductive via between the first and second surfaces of the substrate.

18. The electronic module of claim 17, wherein the element configured to provide thermal management comprises a thermally-conductive adhesive film, a micro-heat pipe structure, or an interleaved-copper thermal-management layer.

19. The electronic module of claim 17, wherein at least one of the first or second semiconductor chip layers is backthinned.

20. The electronic module of claim 17, wherein the first semiconductor chip layer further comprises a bond pad electrically connected to the electrically conductive via.

21. The electronic module of claim 17, further comprising an electrically conductive trace extending along the first surface and configured to electrically connect the electrically conductive via to a bond pad disposed at a horizontal distance from the electrically conductive via.

22. The electronic module of claim 17, wherein the first semiconductor chip layer further comprises a passivation layer disposed over at least a portion of the first or second surface of the first semiconductor chip layer.

23. The electronic module of claim 17, further comprising a conductive bus disposed on a lateral surface of the electronic module and electrically connected to at least one of the first or second semiconductor chip layers.

24. The electronic module of claim 23, wherein at least one of the first or second semiconductor chip layers is electrically connected to the conductive bus by a conductive T-connect structure.

25. The electronic module of claim 24, wherein the conductive T-connect structure is electrically connected to a conductive trace that is electrically connected to an input/output (I/O) pad.

26. A semiconductor chip layer comprising:

a substrate including a first surface and a second surface;

electronic circuitry including a circuit element disposed on the first surface;

a trench in the first surface between the circuit element and the second surface of the substrate, wherein the trench has an interior surface with a dielectric material thereon;

a conductive material disposed within the trench and configured to act as an electrically conductive via between the first surface of the substrate and the second surface of the substrate; and

an element adjacent to at least one of the first or second surfaces of the substrate and configured to provide thermal management for at least one of the substrate or the electronic circuitry.

27. The semiconductor chip layer of claim 26, wherein the element configured to provide thermal management comprises a thermally-conductive adhesive film, a micro-heat pipe structure, or an interleaved-copper thermal-management layer.

28. The semiconductor chip layer of claim 26, wherein the semiconductor chip layer is backthinned.

29. The semiconductor chip layer of claim 26, further comprising a bond pad electrically connected to the electrically conductive via.

30. The semiconductor chip layer of claim 29, further comprising a conductive trace configured to electrically connect the bond pad to the electrically conductive via.

31. The semiconductor chip layer of claim 30, wherein the bond pad is disposed on the first surface at a horizontal distance from the electrically conductive via, and wherein the conductive trace extends along the first surface between the bond pad and the electrically conductive via.

32. The semiconductor chip layer of claim 26, further comprising a passivation layer disposed over at least a portion of the semiconductor chip layer.

33. The semiconductor chip layer of claim 26, further comprising a conductive T-connect structure configured to electrically connect a conductive trace to a conductive bus at a lateral surface of the semiconductor chip layer.

34. The semiconductor chip layer of claim 33, wherein the conductive trace is electrically connected to an input/output (I/O) pad.