Pipeline method and system for switching packets

• US 7,813,367 B2
• Filed: 01/08/2007
• Issued: 10/12/2010
• Est. Priority Date: 05/06/2002
• Status: Expired due to Fees

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Foundry Networks Incorporated (Broadcom, Inc.)
• Inventors: Wong, Aris, Davis, Ian Edward
• Primary Examiner(s): Wong; Warner
• Application Number:
  US11/621,038
• Publication Number:
  US 20090279548A1
• Time in Patent Office: 1,373 Days
• Field of Search: 370/230, 370/235, 370/359, 370/389, 370/392, 370/412, 370/419, 370/463
• US Class Current: 370/419
• CPC Class Codes: H04L 49/1546 using pipelined operation

Abstract

A switching device comprising one or more processors coupled to a media access control (MAC) interface and a memory structure for switching packets rapidly between one or more source devices and one or more destination devices. Packets are pipelined through a series of first processing segments to perform a plurality of first sub-operations involving the initial processing of packets received from source devices to be buffered in the memory structure. Packets are pipelined through a series of second processing segments to perform a plurality of second sub-operations involved in retrieving packets from the memory structure and preparing packets for transmission. Packets are pipelined through a series of third processing segments to perform a plurality of third sub-operations involved in scheduling transmission of packets to the MAC interface for transmission to one or more destination devices.

Claims

1. A system comprising:

a backplane;

a first data pipeline, the first data pipeline coupling a media access control (MAC) interface configured to facilitate receipt and transmission of packets over a physical interface, a receive packet processor configured to perform processing of packets received from the MAC interface, a first memory configured to store packets processed by the receive packet processor, and a backplane manager configured to read the packets from the first memory, to compute an appropriate destination for the packets and to dispatch the packets to the backplane;

a second data pipeline, the second data pipeline coupling a transmission accumulator configured to receive packets from the backplane and to organize the packets for transmission, a second memory configured to store packets processed by the transmission accumulator, a transmit packet processor configured to read the packets from the second memory and to schedule the transmission of packets, and the MAC interface; and

a path for forwarding packets from the first memory to the transmission accumulator without using the backplane.

2. The system of claim 1 wherein the first and second data pipelines comprise a plurality of FIFO structures to provide for pipelined processing of data.

3. The system of claim 2 wherein the receive packet processor, the backplane manager, the transmission accumulator and the transmit packet processor are field programmable gate arrays.

4. The system of claim 2 wherein the receive packet processor, the backplane manager, the transmission accumulator and the transmit packet processor are application specific integrated circuits.

5. The system of claim 1 wherein the first and second memories are dualport memories.

6. A method for switching data, the method comprising:

pipelining data between a media access control (MAC) interface, a receive packet processor coupled to the MAC interface, a first memory, and a backplane manager coupled to the first memory and a backplane, the receive packet processor configured to perform initial processing of received packets, the first memory configured to store packets after processing by the receive packet processor, and the backplane manager configured to compute an appropriate destination and dispatch packets to the backplane; and

pipelining data between a transmission accumulator coupled to the backplane, a second memory, and a transmit packet processor coupled to the second memory and the MAC interface, the transmission accumulator configured to organize packets received from the backplane for transmission to the second memory, and the transmit packet processor configured to schedule the transmission of packets to the MAC interface; and

enabling a packet to be forwarded from the first memory to the transmission accumulator without going through the backplane.