Simulation method

• US 7,840,397 B2
• Filed: 12/04/2006
• Issued: 11/23/2010
• Est. Priority Date: 12/02/2005
• Status: Active Grant

• Current Assignee: Derek Chiou
• Original Assignee: Derek Chiou
• Inventors: Chiou, Derek
• Primary Examiner(s): Jones; Hugh
• Assistant Examiner(s): Luu; Cuong V
• Application Number:
  US11/633,657
• Publication Number:
  US 20070150248A1
• Time in Patent Office: 1,450 Days
• Field of Search: 717/131, 703/14, 703/13, 703/15, 703/16, 703/17, 703/18, 703/19, 703/20, 716/3, 702/117, 702/118, 702/119, 702/120
• US Class Current: 703/20
• CPC Class Codes: G06F 2115/10 Processors
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
• CPC Class Codes: G06F 9/30 Arrangements for executing machine instructions, e.g. instruction decode for executing microinstructions G06F9/22
• CPC Class Codes: G06F 9/30134 Register stacks; shift registers
• CPC Class Codes: G06F 9/3877 using a slave processor, e.g. coprocessor peripheral processor G06F13/12; vector processor G06F15/8053
• CPC Class Codes: G06F 9/4494 data driven

Abstract

A simulator is partitioned into a functional component and a behavior prediction component and the components are executed in parallel. The execution path of the functional component is used to drive the behavior prediction component and the behavior prediction component changes the execution path of the functional component.

Claims

1. A method of performing a simulation of a target digital system, using a simulator, the method comprising:

providing a simulator model of the target digital system partitioned into a functional component that models the target digital system'"'"'s functionality to simulate the target digital system at function levels and a behavior prediction component that models structures required to predict the behavior of the target digital system;

executing the functional and behavior prediction components;

passing an output of the functional component to the behavior prediction component that uses that output to predict behavior;

comparing information from the functional component output with behavior predicted by the behavior prediction component; and

when the output of the functional component is inconsistent with the predicted behavior, providing information from the behavior prediction component to the functional component to correct the functional component output.

2. A method as claimed in claim 1, wherein at least one component is implemented in hardware.

3. A method as claimed in claim 2, wherein the hardware comprises a field programmable gate array (FPGA).

4. A method as claimed in claim 1, wherein the functional component is implemented in software.

5. A method as claimed in claim 4, wherein the behavior prediction component is implemented in hardware.

6. A method as claimed in claim 5, wherein the hardware comprises an FPGA.

7. A method as claimed in claim 6, wherein the simulator simulates a computer system.

8. A method as claimed in claim 1, wherein the behavior prediction component is a timing model that predicts performance.

12. A method as claimed in claim 1, wherein the functional component is implemented in software.

13. A method as claimed in claim 12, wherein the behavior prediction component is implemented in hardware.

14. A method as claimed in claim 13, wherein the hardware comprises an FPGA.

15. A method as claimed in claim 14, wherein the simulator simulates a computer system.

17. A method as claimed in claim 1, wherein the functional component and behavior prediction component are executed in parallel.

9. A method of performing a simulation of a target digital system, using a simulator, the method comprising:

providing a simulator model of the target digital system partitioned into a functional component that models the target digital system'"'"'s functionality to simulate the target digital system at functional levels and a behavior prediction component that models structures required to predict the performance of the target digital system;

executing the functional and behavior prediction components;

passing an instruction trace of the functional component to the behavior prediction component that uses that instruction trace to predict behavior;

comparing information from the functional component instruction trace with behavior predicted by the behavior prediction component; and

when the instruction trace of the functional component is inconsistent with the predicted behavior, providing information from the behavior prediction component to the functional component to correct the functional component instruction trace.

10. A method as claimed in claim 9, wherein at least one component is implemented in hardware.

11. A method as claimed in claim 10, wherein the hardware comprises a field programmable gate array (FPGA).

16. A method as claimed in claim 9, wherein the functional component and behavior prediction component are executed in parallel.