Domino logic circuit and pipelined domino logic circuit
First Claim
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1. A domino logic circuit comprising:
- an input circuit configured to precharge a dynamic node at a first phase of a clock signal and configured to determine a logic level of the dynamic node by performing a logic evaluation of input data at a second phase of the clock signal; and
an output circuit coupled between an output node and the dynamic node, the output circuit being configured to determine a logic level of the output node in response to the clock signal and the logic level of the dynamic node and to maintain the logic level of the output node while the logic evaluation is performed,wherein the output circuit comprises;
a cut-off transistor having a first terminal coupled to the dynamic node, a second terminal coupled to an intermediate node, and a gate terminal receiving the clock signal, anda first transistor having a first terminal coupled to a power supply voltage, a second terminal coupled to the output node, and a gate terminal coupled to the dynamic node;
a second transistor having a first terminal coupled to a power supply voltage, a second terminal coupled to the intermediate node, and a gate terminal coupled to the output node;
a third transistor having a first terminal coupled to the output node, a second terminal coupled to a ground voltage, and a gate terminal coupled to the intermediate node; and
a fourth transistor having a first terminal coupled to the power supply voltage, a second terminal coupled to the output node, and a gate terminal coupled to the intermediate node.
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Abstract
A domino logic circuit includes an input circuit and an output circuit. The input circuit precharges a dynamic node at a first phase of a clock signal. The input circuit determines a logic level of the dynamic node by performing a logic evaluation of input data at a second phase of the clock signal. The output circuit is coupled between an output node and the dynamic node. The output circuit determines a logic level of the output node in response to the clock signal and the logic level of the dynamic node. The output circuit maintains the logic level of the output node while the logic evaluation is performed.
20 Citations
18 Claims
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1. A domino logic circuit comprising:
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an input circuit configured to precharge a dynamic node at a first phase of a clock signal and configured to determine a logic level of the dynamic node by performing a logic evaluation of input data at a second phase of the clock signal; and an output circuit coupled between an output node and the dynamic node, the output circuit being configured to determine a logic level of the output node in response to the clock signal and the logic level of the dynamic node and to maintain the logic level of the output node while the logic evaluation is performed, wherein the output circuit comprises; a cut-off transistor having a first terminal coupled to the dynamic node, a second terminal coupled to an intermediate node, and a gate terminal receiving the clock signal, and a first transistor having a first terminal coupled to a power supply voltage, a second terminal coupled to the output node, and a gate terminal coupled to the dynamic node; a second transistor having a first terminal coupled to a power supply voltage, a second terminal coupled to the intermediate node, and a gate terminal coupled to the output node; a third transistor having a first terminal coupled to the output node, a second terminal coupled to a ground voltage, and a gate terminal coupled to the intermediate node; and a fourth transistor having a first terminal coupled to the power supply voltage, a second terminal coupled to the output node, and a gate terminal coupled to the intermediate node. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A domino logic circuit comprising:
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a precharge transistor configured to precharge a dynamic node at the first phase of a clock signal; a logic network coupled to the dynamic node, the logic network being configured to determine a logic level of the dynamic node by performing a logic evaluation of input data; a pull down transistor coupled between the logic network and a ground voltage to receive the clock signal; a cut-off transistor having a first terminal coupled to the dynamic node, a second terminal coupled to the intermediate node, and a gate terminal receiving the clock signal; a first transistor having a first terminal coupled to a power supply voltage, a second terminal coupled to the intermediate node, and a gate terminal coupled to an output node; a second transistor having a first terminal coupled to the power supply voltage, a second terminal coupled to the output node, and a gate terminal coupled to the dynamic node; a third transistor having a first terminal coupled to the output node, a second terminal coupled to the ground voltage, and a gate terminal coupled to the intermediate node; and a fourth transistor having a first terminal coupled to the power supply voltage, a second terminal coupled to the output node, and a gate terminal coupled to the intermediate node. - View Dependent Claims (9)
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10. A pipelined domino logic circuit comprising:
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a first logic block configured to perform a logic evaluation of first input data in response to a clock signal and configured to generate a first output signal, a logic level of the first output signal being maintained while the logic evaluation is performed; and a second logic block configured to perform a logic evaluation of second input data in response to the clock signal, the second input data including the first output signal, the second logic block being configured to generate a second output signal, a logic level of the second output signal being maintained while the logic evaluation is performed, wherein the first logic block includes; a first input circuit configured to precharge a first dynamic node at a first phase of the clock signal and configured to determine a logic level of the first dynamic node by performing a logic evaluation of input data at a second phase of the clock signal; and a first output circuit coupled between a first output node and the first dynamic node, the first output circuit being configured to generate the first output signal in response to the clock signal and the logic level of the first dynamic node, wherein the first output circuit comprises; a first cut-off transistor having a first terminal coupled to the first dynamic node, a second terminal coupled to a first intermediate node, and a gate terminal receiving the clock signal, and a first transistor having a first terminal coupled to a power supply voltage, a second terminal coupled to the first output node, and a gate terminal coupled to the first dynamic node; a second transistor having a first terminal coupled to a power supply voltage, a second terminal coupled to the intermediate node, and a gate terminal coupled to the output node; a third transistor having a first terminal coupled to the output node, a second terminal coupled to a ground voltage, and a gate terminal coupled to the intermediate node; and a fourth transistor having a first terminal coupled to the power supply voltage, a second terminal coupled to the output node, and a gate terminal coupled to the intermediate node. - View Dependent Claims (11, 12, 13, 14, 15)
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16. A pipelined domino logic circuit comprising a plurality of logic blocks sequentially connected, each logic block comprising:
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an input circuit configured to precharge a dynamic node of the each logic block at a first phase of a clock signal, the input circuit being configured to determine a logic level of the dynamic node of the each logic block by performing a logic evaluation of input data of the each logic block at a second phase of the clock signal, the input data of the each logic block including an output signal of a previous logic block; and an output circuit coupled between an output node of the each logic block and the dynamic node of the each logic block, the output circuit being configured to determine an output signal of the each logic block in response to the clock signal and the logic level of the dynamic node of the each logic block, and provide the output signal of the each logic block to a next logic block, the output circuit being configured to maintain a logic level of the output signal of the each logic block while the logic evaluation is performed, wherein the output circuit comprises; a cut-off transistor having a first terminal coupled to the dynamic node, a second terminal coupled to an intermediate node, and a gate terminal receiving the clock signal, and a first transistor having a first terminal coupled to a power supply voltage, a second terminal coupled to the output node, and a gate terminal coupled to the dynamic node; a second transistor having a first terminal coupled to a power supply voltage, a second terminal coupled to the intermediate node, and a gate terminal coupled to the output node; a third transistor having a first terminal coupled to the output node, a second terminal coupled to a ground voltage, and a gate terminal coupled to the intermediate node; and a fourth transistor having a first terminal coupled to the power supply voltage, a second terminal coupled to the output node, and a gate terminal coupled to the intermediate node. - View Dependent Claims (17, 18)
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Specification