High density interconnect system having rapid fabrication cycle

• US 7,872,482 B2
• Filed: 09/19/2007
• Issued: 01/18/2011
• Est. Priority Date: 05/23/2000
• Status: Expired due to Fees

• Current Assignee: Advantest Corporation
• Original Assignee: Verigy Limited (Advantest Corporation)
• Inventors: Mok, Sammy, Chong, Fu Chiung, Swiatowiec, Frank John, Parekh, Nitin, Litza, Anna, Shan, Zhaohui, Kao, Andrew, Modlin, Douglas, McKay, Douglas
• Primary Examiner(s): Nguyen; Ha Tran T
• Assistant Examiner(s): Nguyen; Tung X.
• Application Number:
  US11/858,064
• Publication Number:
  US 20080246500A1
• Time in Patent Office: 1,217 Days
• Field of Search: 324/765, 324761-762, 324/158.1, 324/760, 438 14- 18, 257/48
• US Class Current: 324/754.07
• CPC Class Codes: G01R 1/073 Multiple probes
• CPC Class Codes: G01R 1/07378 using an intermediate adapter, e.g. space transformers G01R1/07371 takes precedence
• CPC Class Codes: G01R 31/2889 Interfaces, e.g. between probe and tester G01R31/31905 and G01R1/07364 take precedence
• CPC Class Codes: Y10T 29/49117 Conductor or circuit manufacturing
• CPC Class Codes: Y10T 29/49222 forming array of contacts or terminals

Abstract

An improved interconnection system and method is described, such as for connectors, socket assemblies and/or probe card systems. An exemplary system comprises a probe card interface assembly (PCIA) for establishing electrical connections to a semiconductor wafer mounted in a prober. The PCIA comprises a motherboard parallel to the semiconductor wafer having an upper surface and an opposing lower planar mounting surface, a reference plane defined by a least three points located between the lower surface of the motherboard and the wafer, at least one component located below the motherboard mounting surface, and a mechanism for adjusting the planarity of the reference plane with respect to the wafer. A probe chip having a plurality of spring probes extending there from is mountable and demountable from the PCIA, without the need for further planarity adjustment. The interconnection structures and methods preferably provide improved fabrication cycles.

Claims

1. A process, comprising the steps of:

providing an assembly comprising a substrate having a first surface and a second surface opposite the first surface, a plurality of spring probes on the first surface and extending from the first surface to define a plurality of probe tips, a corresponding plurality of electrical contacts located on the second surface, and electrical connections extending from each of the spring probes to each of the corresponding plurality of electrical contacts;

compressing the probe tips against a flat reference surface, wherein the flat reference surface is parallel to any of the first surface and the second surface of the substrate; and

applying heat to the assembly within an oven, such that the compressed probe tips conform to the flat reference surface in response to the applied heat.

2. The process of claim 1, further comprising the step of:

applying at least one plating layer to the probe tips any of before and after the heating step.

3. The process of claim 1, further comprising the step of:

applying at least one plating layer to the probe tips before the heating step, wherein at least one of the plating layers comprises any of nickel, palladium cobalt, rhodium, and gold.

4. The process of claim 1, further comprising the step of:

applying at least one plating layer to the probe tips before the heating step, wherein at least one of the plating layers comprises a thickness of 2 microns to 10 microns.

5. The process of claim 1, further comprising the step of:

applying at least one plating layer to the probe tips after the heating step, wherein at least one of the plating layers comprises a thickness of 5 microns to 50 microns.

6. The process of claim 1, wherein the spring probes comprise any of stress metal springs, flexible springs, compliant springs, and elongate resilient probe elements.

7. The process of claim 1, wherein the heating step comprises heating the assembly to between 175 Centigrade and 225 degrees Centigrade.

8. The process of claim 1, wherein the heating step comprises heating the assembly for a time period of between 1 hour and 3 hours.

9. The process of claim 1, wherein the heating step anneals the spring probes to conform to the flat reference surface.

10. The process of claim 1, further comprising the step of:

cooling the heated assembly to relieve stresses between the substrate and one or more layers of the spring probes.

11. The process of claim 1, wherein the assembly comprises any of a probe chip, a Z-block, and a motherboard.

12. The process of claim 1, wherein the substrate comprises ceramic.

13. A process for planarizing an assembly comprising a substrate having a first surface and a second surface opposite the first surface, a plurality of spring probes on the first surface and extending from the first surface to define a plurality of probe tips, a corresponding plurality of electrical contacts located on the second surface, and electrical connections extending from each of the spring probes to each of the corresponding plurality of electrical contacts, the process comprising the steps of:

compressing the probe tips against a flat reference surface, wherein the flat reference surface is parallel to any of the first surface and the second surface of the substrate; and

applying heat to the assembly within an oven, wherein the compressed probe tips conform to the flat reference surface in response to the applied heat.

14. The process of claim 13, wherein the probe tips further comprise at least one plating layer that is formed any of before and after the planarization.

15. The process of claim 13, wherein the probe tips further comprise at least one plating layer that is formed before the planarization, and wherein at least one of the plating layers comprises any of nickel, palladium cobalt, rhodium, and gold.

16. The process of claim 13, wherein the probe tips further comprise at least one plating layer that is formed before the planarization, and wherein at least one of the plating layers comprises a thickness of 2 microns to 10 microns.

17. The process of claim 13, wherein the probe tips further comprise at least one plating layer that is formed after the planarization, and wherein at least one of the plating layers comprises a thickness of 5 microns to 50 microns.

18. The process of claim 13, wherein the spring probes comprise any of stress metal springs, flexible springs, compliant springs, and elongate resilient probe elements.

19. The process of claim 13, wherein the heating step comprises heating the assembly to between 175 Centigrade and 225 degrees Centigrade.

20. The process of claim 13, wherein the heating step comprises heating the assembly for a time period of between 1 hour and 3 hours.

21. The process of claim 13, wherein the heating step anneals the spring probes to conform to the flat reference surface.

22. The process of claim 13, wherein the planarization further comprises the step of:

cooling the heated assembly to relieve stresses between the substrate and one or more layers of the spring probes.

23. The process of claim 13, wherein the assembly comprises any of a probe chip, a Z-block, and a motherboard.

24. The process of claim 13, wherein the substrate comprises ceramic.