Triple latch flip flop system and method

• US 7,872,492 B2
• Filed: 02/24/2009
• Issued: 01/18/2011
• Est. Priority Date: 06/30/2006
• Status: Expired due to Fees

• Current Assignee: Intellectual Ventures Funding LLC (Intellectual Ventures LLC)
• Original Assignee: Intellectual Ventures Funding LLC (Intellectual Ventures LLC)
• Inventors: Pitkethly, Scott, Masleid, Robert P.
• Primary Examiner(s): Tran; Anh Q
• Application Number:
  US12/391,993
• Publication Number:
  US 20090212815A1
• Time in Patent Office: 693 Days
• Field of Search: None
• US Class Current: 326/27
• CPC Class Codes: H03K 17/162 without feedback from the output circuit to the control circuit
• CPC Class Codes: H03K 17/6872 using complementary field-effect transistors
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 3/356191 with synchronous operation

Abstract

A triple latch flip flop system and method are disclosed. In one embodiment, triple latch flip-flop system includes a pull up latch, a pull down latch, a primary latch and an output. The pull up latch drives a pull up node. The pull down latch driving a pull down node. The primary latch records state of the triple latch flip-flop system. The output for outputting a logic value based upon outputs of the pull up latch, pull down latch and the primary latch.

Claims

1. A triple latch flip-flop system comprising:

a pull up latch operable for driving a pull up node;

a pull down latch coupled to said pull up latch and operable for driving a pull down node;

a first override component configured to control an input of said pull up latch and operable to block data input during a first blocking phase, and a second override component configured to control an input of said pull down latch and operable to block data input during a second blocking phase; and

a primary latch coupled to said pull up latch and said pull down latch and operable for recording a state;

wherein said triple latch flip system is configured to produce an output derived from outputs of said pull up latch, said pull down latch, and said primary latch.

2. The triple latch flip flop system of claim 1, wherein said pull up latch, pull down latch and primary latch comprise static logic gates.

3. The triple latch flip flop system of claim 2, wherein said pull up latch is configured for priority on set.

4. The triple latch flip flop system of claim 2, wherein said pull down latch is configured for priority on reset.

5. The triple latch flip flop system of claim 1, wherein said pull up latch, said pull down latch, and said primary latch comprise dynamic gates.

6. The triple latch flip flop system of claim 5, wherein said pull down latch is configured for priority on reset.

7. The triple latch flip flop system of claim 5, wherein said pull up latch is configured for priority on set.

8. A method comprising:

precharging a triple latch flip flop system;

evaluating data through said triple latch flip flop system;

blocking data in said triple latch flip flop system by disabling an input to a latch of said triple latch flip flop system; and

returning said triple latch flip flop system to a pre-charge state.

9. The method of claim 8, wherein said precharging includes shutting off output drivers and putting a primary latch into a retention mode.

10. The triple latch flip-flop method of claim 8, wherein said precharging includes forcing a pull-up latch into a set state and a pull-down latch into a reset state.

11. The triple latch flip-flop method of claim 8, wherein said precharging drives an output.

12. The triple latch flip-flop method of claim 8, wherein said precharging includes holding an output state until a clock trigger.

13. The triple latch flip-flop method of claim 8, wherein said evaluating includes clocking said triple latch flip flop system.

14. The triple latch flip-flop method of claim 8, wherein said evaluating includes releasing a state hold on a pull-up latch and pull-down latch.

15. The triple latch flip-flop method of claim 8, wherein said evaluating includes resetting a pull up latch.

16. The triple latch flip-flop method of claim 8, wherein said evaluating includes setting a pull down latch.

17. The triple latch flip-flop method of claim 8, wherein said evaluating comprises:

resetting a pull up latch and driving an output node;

setting a primary latch; and

instructing a pull down latch to reset.

18. The method of claim 8, further comprising performing race margin correction.

19. A triple latch flip-flop system comprising:

a pull up latch operable for driving a pull up node;

a pull up override component configured to disable an input of said pull up latch during a data input blocking phase, wherein said pull up override component comprises a skew correcting component operable for correcting clock skew;

a pull down latch coupled to said pull up latch and operable for driving a pull down node; and

a primary latch coupled to said pull up latch and said pull down latch and operable for recording a state.

20. The triple latch flip-flop system of claim 19, further comprising a race suppression component.

21. The triple latch flip-flop system of claim 19, further comprising a noise immunity component.

22. The triple latch flip-flop system of claim 19, further comprising a setup constraint adjuster.

23. The triple latch flip-flop system of claim 19, further comprising a drive enhancement component.

24. The triple latch flip-flop system of claim 19, further comprising a scan component for test.