Architectural enhancements to CPU microcode load mechanism using inter processor interrupt messages
First Claim
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1. A method for loading microcode to a plurality of cores within a processor system comprising:
- loading the microcode to a boot strap processor (BSP) core of the plurality of cores within the processor system;
generating a broadcast inter processor interrupt (IPI) message via the first core, the IPI message causing other cores within the processor system to synchronize their respective microcode with the microcode that is loaded into the BSP core, the synchronizing loading microcode to the plurality of cores without requiring independent loads of microcode to each core.
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Abstract
A method for loading microcode to a plurality of cores within a processor. The method includes loading the microcode to a first core of the plurality of cores within the processor system and generating a broadcast inter process interrupt (IPI) message via the first core. The IPI message causes other cores within the processor system to synchronize respective microcode with the microcode that is loaded into the first core. The synchronizing loads microcode to the plurality of cores without requiring independent loads of microcode to each core.
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12 Claims
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1. A method for loading microcode to a plurality of cores within a processor system comprising:
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loading the microcode to a boot strap processor (BSP) core of the plurality of cores within the processor system; generating a broadcast inter processor interrupt (IPI) message via the first core, the IPI message causing other cores within the processor system to synchronize their respective microcode with the microcode that is loaded into the BSP core, the synchronizing loading microcode to the plurality of cores without requiring independent loads of microcode to each core. - View Dependent Claims (2, 3, 4)
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5. An apparatus for loading microcode to a plurality of cores within a processor system comprising:
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means for loading the microcode to a boot strap processor (BSP) core of the plurality of cores within the processor system; means for generating a broadcast inter processor interrupt (IPI) message via the first core, the IPI message causing other cores within the processor system to synchronize their respective microcode with the microcode that is loaded into the BSP core, the synchronizing loading microcode to the plurality of cores without requiring independent loads of microcode to each core. - View Dependent Claims (6, 7, 8)
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9. An information handling system comprising:
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a processor system, the processor system comprising a plurality of processor cores; and
,a memory coupled to the processor system, the memory storing a microcode load module for loading microcode to the plurality of cores within a processor system, the microcode load module comprising instructions for; loading the microcode to a boot strap processor (BSP) core of the plurality of cores within the processor system; generating a broadcast inter processor interrupt (IPI) message via the first core, the IPI message causing other cores within the processor system to synchronize their respective microcode with the microcode that is loaded into the BSP core, the synchronizing loading microcode to the plurality of cores without requiring independent loads of microcode to each core. - View Dependent Claims (10, 11, 12)
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Specification