Method and apparatus for testing devices using serially controlled resources

• US 7,888,955 B2
• Filed: 09/25/2007
• Issued: 02/15/2011
• Est. Priority Date: 09/25/2007
• Status: Active Grant

• Current Assignee: FormFactor Incorporated
• Original Assignee: FormFactor Incorporated
• Inventors: Berry, Tommie Edward
• Primary Examiner(s): Nguyen; Ha Tran T
• Assistant Examiner(s): BENITEZ ROSARIO, JOSHUA
• Application Number:
  US11/861,223
• Publication Number:
  US 20090079448A1
• Time in Patent Office: 1,239 Days
• Field of Search: 324/158.1, 324754-765
• US Class Current: 324/754.07
• CPC Class Codes: G01R 31/2889 Interfaces, e.g. between probe and tester G01R31/31905 and G01R1/07364 take precedence
• CPC Class Codes: G01R 31/31907 Modular tester, e.g. controlling and coordinating instruments in a bus based architecture

Abstract

Methods and apparatus for testing devices using serially controlled resources have been described. Examples of the invention can relate to an apparatus for testing a device under test (DUT). In some examples, an apparatus can include an integrated circuit (IC) having a serialized input coupled to test circuits, the test circuits selectively communicating test signals with the DUT responsive to a test control signal on the serialized input.

Claims

1. An apparatus for testing a device under test (DUT), comprising:

an integrated circuit (IC) having a serialized input coupled to test circuits, the test circuits selectively communicating test signals with the DUT responsive to a test control signal on the serialized input,

wherein the test circuits comprise;

a shift register, coupled to the serialized input, configured to store bits of the test control signal; and

test resources, coupled to the shift register, configured to provide at least one of a source or a sink of the test signals responsive to the bits.

2. The apparatus of claim 1, wherein each of the test resources comprises one of a digital resource, an analog resource, or a power resource.

3. The apparatus of claim 1, wherein at least one of the test resources is configured to generate a respective at least one of the test signals responsive to at least one of the bits.

4. The apparatus of claim 1, wherein at least one of the test resources is configured to switch a respective at least one of the test signals responsive to at least one of the bits.

5. The apparatus of claim 1, wherein at least one of the test resources comprises a digital resource.

6. The apparatus of claim 1, wherein at least one of the test resources comprises an analog resource.

7. The apparatus of claim 1, wherein at least one of the test resources comprises a power resource.

8. The apparatus of claim 1, wherein at least one of the test resources is a controllable source of test signals to the DUT.

9. A probe card assembly, comprising:

at least one serial control line providing a respective at least one test control signal; and

a plurality of integrated circuits (ICs) serially coupled to form a chain, the chain coupled to the at least one serial control line, the plurality of ICs selectively communicating test signals between test resources and test probes responsive to the at least one test control signal,

wherein each of the plurality of ICs comprises;

at least one control group, each including;

a shift register configured to store bits of a test control signal of the at least one test control signal; and

a plurality of the test resources, coupled to the shift register, configured to provide at least one of a source or a sink of a plurality of the test signals responsive to the bits.

10. The probe card assembly of claim 9, wherein at least one of the plurality of the test resources is configured to generate a respective at least one of the plurality of the test signals responsive to at least one of the bits.

11. The probe card assembly of claim 9, wherein at least one of the plurality of the test resources is configured to switch a respective at least one of the plurality of the test signals responsive to at least one of the bits.

12. The probe card assembly of claim 9, wherein each of the test resources comprises one of a digital resource, an analog resource, or a power resource.

13. The probe card assembly of claim 9, wherein the at least one serial control line comprises a first serial control line providing a first test control signal and a second serial control line providing a second test control signal, and wherein the test resources in the plurality of ICs comprise a first chain of test resources responsive to the first test control signal and a second chain of test resources responsive to the second test control signal.

14. The probe card assembly of claim 13, wherein the first chain of test resources includes digital resources and the second chain of test resources includes power resources.

15. The probe card assembly of claim 9, wherein at least one of the test resources comprises a digital resource.

16. The probe card assembly of claim 9, wherein at least one of the test resources comprises an analog resource.

17. The probe card assembly of claim 9, wherein at least one of the test resources comprises a power resource.

18. The probe card assembly of claim 9, wherein at least one of the test resources is a controllable source of test signals to the test probes.