Semiconductor nanowire with built-in stress
First Claim
1. A semiconductor structure comprising:
- a semiconductor nanowire adjoined to a first semiconductor pad and a second semiconductor pad, wherein a middle portion of said semiconductor nanowire is longitudinally strained;
a gate dielectric surrounding said longitudinally strained middle portion of said semiconductor nanowire;
a dielectric material layer embedding said first and second semiconductor pads, wherein said dielectric material layer is substantially stress-free;
at least one source-side contact via embedded in said dielectric material layer and contacting said first semiconductor pad; and
at least one drain-side contact via embedded in said dielectric material layer and contacting said second semiconductor pad.
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Accused Products
Abstract
A semiconductor nanowire having two semiconductor pads on both ends is suspended over a substrate. Stress-generating liner portions are formed over the two semiconductor pads, while a middle portion of the semiconductor nanowire is exposed. A gate dielectric and a gate electrode are formed over the middle portion of the semiconductor nanowire while the semiconductor nanowire is under longitudinal stress due to the stress-generating liner portions. The middle portion of the semiconductor nanowire is under a built-in inherent longitudinal stress after removal of the stress-generating liners because the formation of the gate dielectric and the gate electrode locks in the strained state of the semiconductor nanowire. Source and drain regions are formed in the semiconductor pads to provide a semiconductor nanowire transistor. A middle-of-line (MOL) dielectric layer may be formed directly on the source and drain pads.
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Citations
24 Claims
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1. A semiconductor structure comprising:
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a semiconductor nanowire adjoined to a first semiconductor pad and a second semiconductor pad, wherein a middle portion of said semiconductor nanowire is longitudinally strained; a gate dielectric surrounding said longitudinally strained middle portion of said semiconductor nanowire; a dielectric material layer embedding said first and second semiconductor pads, wherein said dielectric material layer is substantially stress-free; at least one source-side contact via embedded in said dielectric material layer and contacting said first semiconductor pad; and at least one drain-side contact via embedded in said dielectric material layer and contacting said second semiconductor pad. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A semiconductor structure comprising:
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a semiconductor nanowire adjoined to a first semiconductor pad and a second semiconductor pad, wherein a middle portion of said semiconductor nanowire is longitudinally strained; a gate dielectric surrounding said longitudinally strained middle portion of said semiconductor nanowire; a dielectric material layer embedding said first and second semiconductor pads, wherein said dielectric material layer is substantially stress-free; a gate electrode comprising a conductive material and surrounding said gate dielectric; an insulator layer that includes a first dielectric pedestal and a second dielectric pedestal and underlying said semiconductor nanowire, wherein said first dielectric pedestal adjoins said first semiconductor pad, said second dielectric pedestal adjoins said second semiconductor pad, and said gate electrode adjoins said insulator layer. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23, 24)
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Specification