Integrated circuit that uses a dynamic characteristic of the circuit

• US 7,904,731 B2
• Filed: 01/29/2009
• Issued: 03/08/2011
• Est. Priority Date: 04/16/2002
• Status: Active Grant

• Current Assignee: Massachusetts Institute of Technology
• Original Assignee: Massachusetts Institute of Technology
• Inventors: Gassend, Blaise, Devadas, Srinivas
• Primary Examiner(s): Korzuch; William R
• Assistant Examiner(s): AVERY, JEREMIAH L
• Application Number:
  US12/361,811
• Publication Number:
  US 20090222672A1
• Time in Patent Office: 768 Days
• Field of Search: 726/34
• US Class Current: 713/189
• CPC Class Codes: G06F 21/31 User authentication
• CPC Class Codes: G06F 21/72 in cryptographic circuits
• CPC Class Codes: G06F 21/73 by creating or determining hardware identification, e.g. serial numbers
• CPC Class Codes: G06F 21/77 in smart cards
• CPC Class Codes: G06F 21/79 in semiconductor storage media, e.g. directly-addressable memories
• CPC Class Codes: G06F 21/86 Secure or tamper-resistant housings
• CPC Class Codes: G06F 2221/2103 Challenge-response
• CPC Class Codes: G06F 2221/2121 Chip on media, e.g. a disk or tape with a chip embedded in its case
• CPC Class Codes: G06F 2221/2129 Authenticate client device independently of the user
• CPC Class Codes: G06F 2221/2153 Using hardware token as a secondary aspect
• CPC Class Codes: G06Q 20/3674 involving authentication
• CPC Class Codes: G09C 1/00 Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system cryptographic typewriters G09C3/00
• CPC Class Codes: H01L 2223/54433 containing identification or tracking information
• CPC Class Codes: H01L 2223/5444 for electrical read out
• CPC Class Codes: H01L 2223/54473 for use after dicing
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 23/576 using active circuits
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H04L 2209/34 Encoding or coding, e.g. Huffman coding or error correction
• CPC Class Codes: H04L 2209/42 : Anonymization, e.g. involving pseudonyms
• CPC Class Codes: H04L 9/0897 : involving additional devices, e.g. trusted platform module [TPM], smartcard or USB
• CPC Class Codes: H04L 9/3278 : using physically unclonable functions [PUF]

Abstract

An integrated circuit has a first component that has a dynamic characteristic that varies among like integrated circuits, for example, among integrated circuits fabricated using the same lithography mask. Operating the first component produces an output that is dependent on the dynamic characteristic of the first component. A digital value associated with the integrated circuit is generated using the output of the first component, and then the generated digital value is used in operation of the integrated circuit.

Claims

1. An integrated circuit device comprising:

a challengeable device-specific response generation circuit including circuitry for accepting a multiple-bit challenge value;

circuitry for implementing a plurality of bistable logic modules, wherein each bistable logic module has an input for accepting an excitation signal and an output with two stable logic output states;

each bistable logic module is configured to receive an excitation signal and after a time period from receiving the excitation signal reach a stable output in one of the two stable logic output states, and

each bistable logic module is fabricated such that fabrication variation from device to devices fabricated according to the module design provides a device-specific likelihood of reaching each stable logic output state;

circuitry for providing a response value based on the challenge value and outputs of multiple of the bistable logic modules; and

circuitry coupled to the response generation circuitry for using stored redundant bits to correct the response value to a previously generated responses and using the corrected responses as a cryptographic key.

2. The circuit of claim 1 wherein each bistable logic module has a module design that ideally provides an equal likelihood of reaching each stable logic output states.

3. The circuit of claim 1 wherein the circuitry for implementing the bistable logic modules includes at least two delay paths for passing the excitation signal to a bistable arbiter circuit, wherein the bistable arbiter circuit is configured to accept the excitation signal over the delay paths and to set its output based on over which path the excitation signal arrives first at the bistable arbiter circuit.

4. The circuit of claim 3 wherein the circuitry for implementing the plurality of bistable logic modules is configurable to implement different logic modules of the plurality of bistable logic modules based on different challenge values.

5. The circuit of claim 4 wherein the circuit is configurable by configuring the delay paths according to the challenge value.

6. The circuitry of claim 1 wherein the challenge value is used to select a subset of the bistable logic modules according the output of which the response value is determined.

7. An integrated circuit device comprising:

a challengeable device-specific response generation circuit including circuitry for accepting a multiple-bit challenge value;

circuitry for implementing a plurality of bistable logic modules, wherein each bistable logic module has an input for accepting an excitation signal and an output with two stable logic output states;

each bistable logic module is configured to receive an excitation signal and after a time period from receiving the excitation signal reach a stable output in one of the two stable logic output states, and

each bistable logic module is fabricated such that fabrication variation from device to devices fabricated according to the module design provides a device-specific likelihood of reaching each stable logic output state;

circuitry for providing a response value based on the challenge value and outputs of multiple of the bistable logic modules; and

circuitry coupled to the response generation circuitry configured to process the generated response to form a cryptographic key.

8. The integrated circuit device of claim 7 wherein the circuitry coupled to the response generation circuitry is configured to accept stored redundant bits and includes an error corrector for combining the generated response and the accepted redundant bits to recover a prior generated output of the response generation circuitry to form the cryptographic key.