Integrated circuit and method for monitoring and controlling power and for detecting open load state

• US 7,908,101 B2
• Filed: 02/28/2008
• Issued: 03/15/2011
• Est. Priority Date: 02/28/2007
• Status: Active Grant

• Current Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Inventors: Mirowski, Marian, Burlak, Gary Joseph
• Primary Examiner(s): Feliciano; Eliseo Ramos
• Assistant Examiner(s): Desta; Elias
• Application Number:
  US12/038,936
• Publication Number:
  US 20080204033A1
• Time in Patent Office: 1,111 Days
• Field of Search: 702/58, 702/64, 702/79, 702/107, 363/74, 324/504, 323/234, 320/161, 320/162, 318/599
• US Class Current: 702/64
• CPC Class Codes: H02H 3/12 responsive to underload or no-load for motors H02H7/0827

Abstract

An integrated circuit and method for monitoring and controlling power and for identifying an open circuit state at an output port is disclosed. A circuit is implemented to determine whether an open circuit state exists based on a comparison of data received from the output port and attached loads. The data received from the output port and attached loads is compared to a minimum open circuit current value of the output port, wherein the minimum open circuit current value is based on the hardware characteristics of the output port and attached loads. A possible open circuit state at the output port is reported based on the comparison.

Claims

1. A method for identifying an open circuit state at an output port configured to provide power to an electrical device coupled to the output port, comprising:

(1) storing a minimum open circuit current value of the output port in a memory device, the minimum open circuit current value being based on a hardware characteristic of the output port;

(2) measuring a current value at the output port for a selected number of times at selected time intervals;

(3) storing the measured current values in the memory device;

(4) selecting a subset of current values;

(5) calculating an average of the selected subset of the current values;

(6) comparing the average current value to the minimum open circuit current value; and

(7) identifying the open circuit state at the output port based on the comparison.

2. The method according to claim 1, further comprising reporting a possible open circuit state at the output port if the average current value is less than the minimum open circuit current value.

3. The method according to claim 1, further comprising:

repeating (2)-(7) as recited in claim 1 and reporting a possible open circuit state at the output port if the average current value is less than the minimum open circuit current value;

incrementing a count value for successive possible open circuit states at the output port;

reporting a validated open circuit state at the output port if the count value exceeds an open circuit validation threshold count; and

resetting the count value if the average current value exceeds the minimum current value.

4. The method according to claim 3, further comprising removing power from the output port if a validated open circuit state is reported.

5. The method according to claim 1, wherein the subset of the current values are selected by filtering ones of the measured current values outside an acceptable range of current values.

6. The method according to claim 1, wherein the subset of the current values are selected by filtering transient ones of the measured current values.

7. The method according to claim 1, wherein the subset of the current values are selected by filtering the ones of the measured current values outside a standard deviation of a previously calculated average current value.

8. A method for identifying an open circuit state at one of a plurality of output ports each configured to provide power to an electrical device, the method comprising:

(1) determining a learned open circuit current value of the output port, the learned open circuit current value being based on a plurality of measured learn-phase load currents at the output port;

(2) storing the learned open circuit current value in a memory device;

(3) measuring a current value at the output port for a selected number of times at selected time intervals;

(4) storing the measured current values in the memory device;

(5) selecting, by a processor, a subset of the current values;

(6) calculating, by the processor, an average of the selected subset of the current values;

(7) comparing the average current value to the learned open circuit current value; and

(8) identifying the open circuit state based on the comparison.

9. The method according to claim 8, wherein determining the learned open circuit current comprises:

measuring the learn-phase load current at the output port for a selected number of times at selected time intervals;

storing the measured learn-phase load current values in the memory device;

selecting, by the processor, a subset of the learn-phase load current values; and

generating the learned open circuit current from the average of the subset of the learn-phase current values.

10. The method according to claim 8, further comprising

repeating (3)-(8) as recited in claim 8 and reporting a possible open circuit state at the output port if the average current value is less than the learned open circuit current value;

incrementing a count value for successive possible open circuit states at the output port;

reporting a validated open circuit state at the output port if the count value exceeds an open circuit validation threshold count, the validated open circuit state indicating an open load condition at the output port; and

resetting the count value if the average current value exceeds the learned open circuit current value.

11. The method according to claim 10, further comprising:

determining if the output port has a symmetrical output port, the symmetrical output port being equivalent to the output port;

determining, by the processor, the average load current at the symmetric output port;

comparing, by the processor, the symmetric output port'"'"'s average load current to the output port'"'"'s average load current; and

determining, by the processor, a percentage difference between the average load current at the output port and the average load current at the symmetric output port.

12. The method according to claim 11, further comprising reporting a possible unbalanced load condition if the percentage difference exceeds a maximum percentage.

13. The method according to claim 12, further comprising:

incrementing a count value for successive possible unbalanced load conditions at the output port;

reporting a validated unbalanced load condition at the output port if the count value exceeds an unbalanced load validation threshold count;

resetting the count value if the percentage difference is less than the maximum percentage.

14. The method according to claim 13, further comprising removing power from the output port if a validated unbalanced load condition is reported.

15. An integrated circuit device for monitoring and controlling an output port adapted to provide electrical power to a load, the integrated circuit device identifying an open circuit state at the output port, comprising:

a memory;

a processor electrically coupled to the memory, the processor configured to store data in, and receive data from, the memory;

a switched power control circuit electrically coupled to the load, the switched power control circuit configured to control the electrical power delivered to the load by varying a duty cycle responsive to a power control signal received from the processor;

a current sense circuit electrically coupled and configured to measure current flowing to the load and provide a current sense signal representative of the measured current to the processor, the current sense circuit further configured to provide an open circuit state signal to the processor when the measured current is less than a minimum open circuit current; and

the processor configured to store data representative of the current sense signal in the memory, the processor further configured to provide the power control signal to the switched power control circuit responsive to the current sense signal, the processor further configured to report the open circuit state responsive to the open circuit signal.

16. The integrated circuit device of claim 15, wherein the power control signal is a pulse width modulated signal for controlling the duty cycle of the switched power control circuit.

17. The integrated circuit device of claim 15, further comprising varying, by the processor, the duty cycle of the switched power control circuit to remove power from the output port responsive to the current signal indicating that the measured current flowing through the load exceeds a maximum current.

18. The integrated circuit device of claim 15, further comprising varying, by the processor, the duty cycle of the switched power control circuit to remove power from the output port responsive to the open circuit signal.

19. The integrated circuit device of claim 15, wherein the current sense circuit further comprises:

a reference current circuit configured to provide a reference current;

a first comparator circuit configured to compare the measured current flowing through the load to the reference current, the comparator circuit further configured to provide the current sense signal responsive to the comparison.

20. The integrated circuit device of claim 15, further comprising a voltage sense circuit configured to measure the voltage across the load.

21. The integrated circuit device of claim 15, further comprising a network interface circuit configured to facilitate communication between the processor and external devices.

22. A integrated circuit device for monitoring and controlling a plurality of output ports each adapted to provide electrical power to a respective load, the integrated circuit identifying an open circuit state at one of the output ports, comprising:

a memory;

a processor electrically coupled to the memory, the processor configured to store data in, and receive data from, the memory;

a plurality of switched power control circuits each electrically coupled to a respective load, the switched power control circuit configured to control the electrical power delivered to the load by varying a duty cycle responsive to a power control signal from the processor;

a plurality of current sense circuits each electrically coupled to a respective load, the current sense circuit configured to measure the current flowing through the load and provide a current sense signal representative of the measured current to the processor; and

the processor configured to store data representative of the current sense signal in the memory, the processor further configured to provide the power control signal to the switched power control circuit responsive to the current sense signal, the processor including (a) a learn operating mode which calculates a learned open circuit current value at the output port based on a plurality of current sense signals during a learning stage, and (b) a monitoring mode which calculates an average current value at the output port based on a plurality of current sense signals during a steady state, the processor further configured to report an open circuit state at the output port responsive to a comparison of the average current value to the learned open circuit current value.

23. The integrated circuit device of claim 22, wherein the power control signal is a pulse width modulated signal configured to control the duty cycle of the switched power control circuit.

24. The integrated circuit device of claim 22, wherein the duty cycle of the switched power control circuit is varied by the power control signal from the processor to remove power from the output port.

25. The integrated circuit device of claim 22, wherein the processor reports the open circuit state when the average current value is less than the learned open circuit current value.

26. The integrated circuit device of claim 22, wherein the current sense circuit further comprises:

a reference current circuit configured to provide a reference current;

a first comparator circuit configured to compare the measured current flowing through the load to the reference current, the comparator circuit configured to provide the current sense signal responsive to the comparison.

27. The integrated circuit device of claim 22, further comprising a network interface circuit configured to facilitate communication between the processor and external devices.