Adaptable detection threshold for RFID tags and chips

• US 7,917,088 B2
• Filed: 02/02/2007
• Issued: 03/29/2011
• Est. Priority Date: 04/13/2004
• Status: Active Grant

• Current Assignee: Impinj, Inc.
• Original Assignee: Impinj, Inc.
• Inventors: Hyde, John D., Sundstrom, Kurt E.
• Primary Examiner(s): Anderson; Matthew D.
• Assistant Examiner(s): GONZALES, APRIL GUZMAN
• Application Number:
  US11/670,587
• Publication Number:
  US 20070126584A1
• Time in Patent Office: 1,516 Days
• Field of Search: 455/41.2, 455/336, 340/572.1, 340/10.2, 340/10.42, 340/505, 340/5.61, 342/42, 342/50, 342/44, 331/1.A, 235/492, 235/380, 327/157, 327/159
• US Class Current: 455/41.2
• CPC Class Codes: H04B 5/48 Transceivers
• CPC Class Codes: H04B 5/77 for interrogation

Abstract

RFID tags, tag circuits, and methods are provided that reduce at least in part the distortion to received wireless signals, which is caused by interference in the environment. Two or more thresholds are used to digitize the received signal implemented by two or more demodulators. Multiple low pass and digital filters may be implemented with the demodulators, allowing removal of narrow pulses caused by the interference and reduction of beat tone amplitude.

Claims

1. A method for a circuit of a Radio Frequency Identification (RFID) tag, the method including:

receiving a modulated wireless RF input signal;

deriving an analog output signal responsive to the modulated wireless RF input signal at an envelope detector;

deriving a first unfiltered digital output signal responsive to the analog output signal and to a first analog decision threshold at a first slicer circuit;

deriving a second unfiltered digital output signal responsive to the analog output signal and to a second analog decision threshold at a second slicer circuit; and

deriving a filtered digital output signal at a selection circuit by selecting one of the first and second unfiltered digital outputs at a multiplexer of the selection circuit and configuring the multiplexer by a digital decision circuit based on a performance criterion.

2. The method of claim 1, wherein at least a portion of the circuitry for the first and second slicer circuits is common to both.

3. The method of claim 1, further comprising:

deriving an additional unfiltered digital output signal by at least one additional slicer circuit responsive to the analog output signal and to an additional analog decision threshold.

4. The method of claim 1, wherein the selection circuit includes a digital filter responsive to at least one of the unfiltered digital outputs.

5. The method of claim 4, wherein the digital filter is a narrow pulse digital filter.

6. The method of claim 1, wherein

the performance criterion includes at least one from a set of:

a valid frame synch, a valid preamble, and a valid command.

7. The method of claim 1, wherein

the envelope detector contains a low pass analog filter.

8. The method of claim 1, wherein the digital filtered output signal includes a number.

9. The method of claim 1, wherein the digital filtered output signal includes a signal.

10. The method of claim 1, wherein the selection circuit includes a plurality of digital filters responsive to at least one of the unfiltered digital outputs and the method further comprises:

setting one of the digital filters to detect all data rates; and

setting at least one of the remaining filters to detect a subset of the data rates.

11. The method of claim 10, in which

setting one of the plurality of filters to detect all data rates includes setting an aperture of the filter to a minimum width.

12. A method for a circuit of a Radio Frequency Identification (RFID) tag, the method including:

receiving a modulated wireless RF input signal;

deriving an analog output signal responsive to the modulated wireless RF input signal at an envelope detector;

applying power to a first and second slicer circuits until a performance criterion is met, the performance criterion signifying that a frame synch has been detected;

selecting one of the first and second slicer circuits at a selection circuit to generate an unfiltered digital output;

discontinuing applying power to the unselected one of the first and second slicer circuits; and

deriving a filtered digital output signal at the selection circuit.

13. The method of claim 12, in which

selecting one of the first and second slicer circuits is performed by:

detecting a falling edge of a symbol following an RTcal signal; and

if a higher threshold slicer circuit has detected the falling edge, using the higher threshold slicer circuit to generate the unfiltered digital output,

else if a lower threshold slicer circuit has detected the falling edge, using the lower threshold slicer circuit to generate the unfiltered digital output.

14. The method of claim 12, further comprising:

determining a data rate of the analog output signal; and

adjusting a clock frequency of the selection circuit based on the determined data rate.

15. The method of claim 14, in which

adjusting the selection circuit clock frequency includes reducing the clock frequency if the data rate is below a predefined value.

16. The method of claim 14, in which

the selection circuit clock frequency is adjusted based on which slicer circuit is selected to generate the unfiltered digital output.