Stress enhanced MOS circuits
First Claim
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1. A stress enhanced MOS circuit, comprising:
- a semiconductor substrate;
a gate insulator overlying the semiconductor substrate;
a gate electrode overlying the gate insulator, the gate electrode having side walls and comprising a layer of polycrystalline silicon having a first thickness in contact with the gate insulator and a layer of electrically conductive stressed material having a second thickness greater than the first thickness, the layer of electrically conductive stressed material overlying and contacting the layer of polycrystalline silicon; and
a stress liner layer overlying the side walls.
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Abstract
A stress enhanced MOS circuit is provided. The stress enhanced MOS circuit comprises a semiconductor substrate and a gate insulator overlying the semiconductor substrate. A gate electrode overlies the gate insulator; the gate electrode has side walls and comprising a layer of polycrystalline silicon having a first thickness in contact with the gate insulator and a layer of electrically conductive stressed material having a second thickness greater than the first thickness overlying the layer of polycrystalline silicon. A stress liner overlies the side walls of the gate electrode.
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Citations
12 Claims
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1. A stress enhanced MOS circuit, comprising:
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a semiconductor substrate; a gate insulator overlying the semiconductor substrate; a gate electrode overlying the gate insulator, the gate electrode having side walls and comprising a layer of polycrystalline silicon having a first thickness in contact with the gate insulator and a layer of electrically conductive stressed material having a second thickness greater than the first thickness, the layer of electrically conductive stressed material overlying and contacting the layer of polycrystalline silicon; and a stress liner layer overlying the side walls. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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Specification