Memory with correlated resistance

• US 7,969,783 B2
• Filed: 06/15/2007
• Issued: 06/28/2011
• Est. Priority Date: 06/15/2007
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Baker, R. Jacob
• Primary Examiner(s): Luu; Pho M.
• Application Number:
  US11/818,983
• Publication Number:
  US 20080310228A1
• Time in Patent Office: 1,474 Days
• Field of Search: 365/185.17, 365/185.09, 365/185.23, 365/230.03, 365/185.29, 365/185.33
• US Class Current: 365/185.17
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 11/5678 using amorphous/crystalline phase transition storage elements
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 2211/5644 Multilevel memory comprising counting devices

Abstract

A system or device including a memory device, as well as a method of operating the memory device. Such a method includes writing a plurality of data values to a plurality of data locations. The plurality of data locations may be coupled to one another in a series, and the plurality of data values may be sequentially written to the plurality of data locations, starting with the data location at an end of the series and then sequentially writing to each adjacent data location.

Claims

1. A method of operating a memory device, comprising:

writing a plurality of data values to a plurality of data locations, wherein the plurality of data locations are coupled to one another in a series, and wherein the plurality of data values are sequentially written to the plurality of data locations, starting with the data location at an end of the series and then sequentially writing to each adjacent data location; and

reading from one of the data locations by sensing a current through the data location with a delta-sigma modulator.

2. The method of claim 1, wherein each of the plurality of data locations comprises a floating gate transistor.

3. The method of claim 2, wherein a source of each floating gate transistor is coupled to a drain of an adjacent floating gate transistor.

4. The method of claim 3, wherein writing comprises first writing to a floating gate transistor at the end of the series before writing to the other floating gate transistors.

5. The method of claim 4, wherein writing comprises writing to every floating gate transistor in a sequence based on the number of floating gate transistors between each floating gate transistor and the floating gate transistor at the end of the series.

6. The method of claim 1, wherein writing comprises:

adjusting a parameter of one of the data locations by an increment;

reading the value stored by the one of the data locations;

determining whether the value stored corresponds to a value to be written; and

if the value stored does not correspond to the value to be written, adjusting the parameter by another increment.

7. The method of claim 6, wherein the parameter is a charge on a floating gate transistor.

8. The method of claim 6, wherein reading comprises sensing a current through the one of the data locations with a delta-sigma modulator.

9. The method of claim 1, comprising erasing the plurality of data locations generally simultaneously.

10. The method of claim 1, wherein the value of a source-side resistance of the data location, when reading, is generally equal to a source-side resistance of the data location, when writing.

11. The method of claim 1, comprising transmitting data read from the data location to a processor of a computer system.

12. A method of operating an integrated semiconductor device, comprising:

erasing a plurality of floating gate transistors coupled to each other in a series source-to-drain; and

writing to each of the plurality of floating gate transistors one at a time, in sequence, starting with a floating gate transistor at an end of the series and finishing with a floating gate transistor at the other end of the series, wherein writing comprises incrementally adjusting a charge on each of the floating gate transistors and sensing whether the charge corresponds to a desired value.

13. The method of claim 12, wherein the plurality of floating gate transistors are erased generally simultaneously.

14. The method of claim 12, comprising reading from one of the plurality of floating gate transistors, wherein reading is performed before any of the floating gate transistors is written to again.

15. The method of claim 12, comprising reading from one of the plurality of floating gate transistors with a delta-sigma modulator.

16. The method of claim 15, wherein reading comprises transmitting a bit-stream from the delta-sigma modulator to a counter.

17. The method of claim 15, wherein reading comprises truncating a least significant bit from an output of the counter.

18. A method of operating a memory device, comprising:

fixing a resistance value for each of a plurality of data locations coupled to one another in a series via writing a data value to a data location at an end of plurality of data locations and then sequentially writing a data value to each adjacent data location such that a resistance in each of the data locations is fixed as each subsequent data location is written to; and

reading the data values from the plurality of data locations such that the plurality of data values written to the plurality of data locations does not change between writing the plurality of data values and reading the data values.

19. The method of claim 18, wherein each of the plurality of data locations comprises a floating gate transistor.

20. The method of claim 19, wherein a source of each floating gate transistor is coupled to a drain of an adjacent floating gate transistor.

21. The method of claim 20, wherein writing comprises first writing to a floating gate transistor at the end of the series before writing to the other floating gate transistors.

22. The method of claim 18, comprising reading from one of the data locations by sensing a current through the data location with a delta-sigma modulator.