Memory with correlated resistance
First Claim
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1. A method of operating a memory device, comprising:
- writing a plurality of data values to a plurality of data locations, wherein the plurality of data locations are coupled to one another in a series, and wherein the plurality of data values are sequentially written to the plurality of data locations, starting with the data location at an end of the series and then sequentially writing to each adjacent data location; and
reading from one of the data locations by sensing a current through the data location with a delta-sigma modulator.
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Abstract
A system or device including a memory device, as well as a method of operating the memory device. Such a method includes writing a plurality of data values to a plurality of data locations. The plurality of data locations may be coupled to one another in a series, and the plurality of data values may be sequentially written to the plurality of data locations, starting with the data location at an end of the series and then sequentially writing to each adjacent data location.
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Citations
22 Claims
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1. A method of operating a memory device, comprising:
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writing a plurality of data values to a plurality of data locations, wherein the plurality of data locations are coupled to one another in a series, and wherein the plurality of data values are sequentially written to the plurality of data locations, starting with the data location at an end of the series and then sequentially writing to each adjacent data location; and reading from one of the data locations by sensing a current through the data location with a delta-sigma modulator. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method of operating an integrated semiconductor device, comprising:
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erasing a plurality of floating gate transistors coupled to each other in a series source-to-drain; and writing to each of the plurality of floating gate transistors one at a time, in sequence, starting with a floating gate transistor at an end of the series and finishing with a floating gate transistor at the other end of the series, wherein writing comprises incrementally adjusting a charge on each of the floating gate transistors and sensing whether the charge corresponds to a desired value. - View Dependent Claims (13, 14, 15, 16, 17)
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18. A method of operating a memory device, comprising:
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fixing a resistance value for each of a plurality of data locations coupled to one another in a series via writing a data value to a data location at an end of plurality of data locations and then sequentially writing a data value to each adjacent data location such that a resistance in each of the data locations is fixed as each subsequent data location is written to; and reading the data values from the plurality of data locations such that the plurality of data values written to the plurality of data locations does not change between writing the plurality of data values and reading the data values. - View Dependent Claims (19, 20, 21, 22)
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Specification