FPGA configuration protection and control using hardware watchdog timer

• US 7,971,051 B2
• Filed: 09/27/2007
• Issued: 06/28/2011
• Est. Priority Date: 09/27/2007
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Paul, Steven, Garcia, Arturo, Capellaro, Mark
• Primary Examiner(s): Stoynov; Stefan
• Application Number:
  US11/905,057
• Publication Number:
  US 20090085603A1
• Time in Patent Office: 1,370 Days
• Field of Search: 713/1, 713/100, 326/38, 326/39, 714/725, 716/16, 716/116, 712/1, 712/100
• US Class Current: 713/100
• CPC Class Codes: H03K 19/17764 for reliability

Abstract

An apparatus and method provides automatic reconfiguration of an FPGA, such as in case of lost configuration or configuration error, and software-controlled reconfiguration may be provided that does not require the use of additional devices. An apparatus for FPGA configuration protection comprises watchdog signal generator circuitry in the FPGA configured to output a watchdog signal when the FPGA is properly configured and watchdog circuitry configured to receive the watchdog signal and to initiate reconfiguration of the FPGA if the watchdog signal is not received for or within a predetermined time. The circuitry in the FPGA may be configured to receive a signal from a processor and to output the watchdog signal when the signal from the processor is received.

Claims

1. An apparatus for FPGA configuration protection comprising:

watchdog signal generator circuitry in the FPGA configured to output a watchdog signal when the FPGA is properly configured;

watchdog circuitry configured to receive the watchdog signal, to initiate reconfiguration of the FPGA with a reset signal if the watchdog signal is not received for or within a predetermined time, and to repeat until a successful configuration occurs;

circuitry in the FPGA configured to receive a signal from a processor and to output the watchdog signal when the signal from the processor is received; and

a multiplexer which transfers watchdog signal responsibilities to the processor after the processor is released from reset.

2. The apparatus of claim 1, wherein the watchdog circuitry is external to the FPGA.

3. The apparatus of claim 1, wherein the watchdog circuitry comprises a timer.

4. A method of FPGA configuration protection comprising:

initiating configuration of the FPGA;

upon successful completion of configuration of the FPGA, outputting a signal from the FPGA;

if the signal from the FPGA is received, not initiating reconfiguration of the FPGA;

if the signal from the FPGA is not received for or within a predetermined time, initiating automatic reconfiguration of the FPGA, repeating until a successful configuration occurs;

receiving a signal from a processor;

outputting the signal from the FPGA when the signal from the processor is received,

outputting the signal from the FPGA after configuration of the FPGA is completed until the processor is released from reset;

switching responsibility of outputting the signal to the processor; and

initiating software-controlled reconfiguration of the FPGA when the processor wishes by allowing a watchdog device to trip.