Active pixel sensor with reduced fixed pattern noise

• US 7,973,843 B2
• Filed: 03/27/2009
• Issued: 07/05/2011
• Est. Priority Date: 04/23/1999
• Status: Expired due to Term

• Current Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Original Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Inventors: Andersson, Anders, Barna, Sandor L.
• Primary Examiner(s): Giles; Nicholas G
• Application Number:
  US12/413,134
• Publication Number:
  US 20100079643A1
• Time in Patent Office: 830 Days
• Field of Search: 348/316, 348/317, 348/299, 348/298, 348/297, 348/296, 348/311, 348/302, 348/314, 348/241
• US Class Current: 348/296
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/14654 Blooming suppression
• CPC Class Codes: H01L 27/14656 Overflow drain structures
• CPC Class Codes: H04N 25/616 involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
• CPC Class Codes: H04N 25/65 applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array

Abstract

An image sensor includes pixels each of which is designed to transfer charge, accumulated in a photoactive region of the pixel during a first period, through a second active region of the pixel to a power supply node, and to transfer charge, accumulated in the photoactive region during a second period, through the second active region to a sense node in the pixel. Passing charge through the second active region prior to transferring it either to the power supply node or the sense node can help reduce fixed pattern noise. The image sensor can be operated in snap-shot mode.

Claims

1. A pixel array, comprising:

a plurality of pixels, each pixel including;

a photoactive region and an active region separated by a first transfer gate, anti-blooming and storage regions selectively connectable to the active region and separated from the active region by second and third transfer gates, respectively, and a reset gate selectively connectable to the storage region; and

a controller operable to control the transfer and reset gates of the plurality of pixels, wherein the controller is operable to;

set the active region of a pixel to a predetermined charge level;

cause charge accumulated in the photoactive region of the pixel during a non-charge integration period to be transferred to the active region of the pixel;

cause charge from the active region to be transferred to the anti-blooming region of the pixel;

reset the active region to the predetermined charge level;

cause charge accumulated in the photoactive region during a charge integration period to be transferred to the active region of the pixel; and

cause charge from the active region to be transferred to the storage region of the pixel.

2. The pixel array of claim 1, wherein the controller is operable to provide control signals to the transfer gates in each pixel to cause a predetermined amount of charge to be transferred to a respective active region prior to a charge transfer from a respective photoactive region to a respective active region.

3. The pixel array of claim 1, wherein the controller is operable to provide control signals to each pixel to cause the pixels to transfer charge accumulated in their photoactive regions during a common integration period to their respective storage nodes at substantially the same time.

4. The pixel array of claim 1, wherein the controller is operable to control the transfer and reset gates of each of the plurality of pixels in any one of four modes:

a first mode in which charge is accumulated in each photoactive region;

a second mode in which charge is transferred from the photoactive region through the first transfer gate to the active region;

a third mode in which charge is transferred from the active region through the second transfer gate to the anti-blooming region; and

a fourth mode in which charge is transferred from the active region through the third transfer gate to the storage region.