Post passivation interconnection process and structures

• US 8,018,060 B2
• Filed: 01/16/2008
• Issued: 09/13/2011
• Est. Priority Date: 09/09/2004
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung, Chou, Chien-Kang, Chou, Chiu-Ming
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US12/014,812
• Publication Number:
  US 20080128910A1
• Time in Patent Office: 1,336 Days
• Field of Search: 257/359, 257/536, 257/537, 257/758, 257/759, 257/760, 257/773
• US Class Current: 257/758
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 23/3171 the coating being directly applied to the semiconductor body, e.g. passivation layer H01L23/3178 takes precedence
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/5228 Resistive arrangements or effects of, or between, wiring layers other resistive arrangements H01L23/647
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/04953 TaN
• CPC Class Codes: H01L 2924/05042 Si3N4
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/19015 including thin film passive components
• CPC Class Codes: H01L 2924/19041 being a capacitor
• CPC Class Codes: H01L 2924/19042 being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/19104 : on the semiconductor or solid-state device, i.e. passive-on-chip
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

A system and method for forming post passivation metal structures is described. Metal interconnections and high quality electrical components, such as inductors, transformers, capacitors, or resistors are formed on a layer of passivation, or on a thick layer of polymer over a passivation layer.

Claims

1. An integrated circuit structure comprising:

a silicon substrate;

a transistor in and on said silicon substrate;

a first dielectric layer over said silicon substrate;

a metallization structure over said first dielectric layer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer;

a second dielectric layer over said first dielectric layer and between said first and second metal layers;

a metal trace over said silicon substrate;

a contact pad over said silicon substrate;

a passivation layer over said metallization structure, said first and second dielectric layers and said metal trace, wherein a first opening in said passivation layer is over a contact point of said contact pad, and said contact point is at a bottom of said first opening, wherein said passivation layer comprises a nitride;

a polymer layer on a top surface of said passivation layer, wherein said polymer layer has a thickness between 2 and 150 micrometers, wherein a second opening in said polymer layer is over said contact point and over a region of said top surface of said passivation layer;

a coil on said polymer layer, wherein said coil comprises a glue layer, a copper seed layer having a thickness between 0.2 and 1 micrometer on said glue layer, and an electroplated copper layer having a thickness between 3 and 20 micrometers on said copper seed layer, wherein there is an undercut with an edge of said glue layer recessed from an edge of said electroplated copper layer, wherein a first product of resistance of a first section of said coil times capacitance of said first section is at least 100 times smaller than a second product of resistance of a second section of said metal trace times capacitance of said second section, wherein said first section has a same length as said second section;

a metal interconnect on said polymer layer, said region of said top surface of said passivation layer, and said contact point, wherein said metal interconnect is connected to said contact point through said first and second openings; and

a solder bump connected to said metal interconnect.

2. The integrated circuit structure of claim 1, wherein said second dielectric layer comprises a silicon-based oxide.

3. The integrated circuit structure of claim 1, wherein said glue layer comprises titanium.

4. The integrated circuit structure of claim 1, wherein said glue layer comprises a titanium-tungsten alloy.

5. The integrated circuit structure of claim 1, wherein said glue layer comprises a titanium-containing layer.

6. The integrated circuit structure of claim 1, wherein said glue layer comprises chromium.

7. The integrated circuit structure of claim 1, wherein said coil further comprises a nickel-containing layer on said electroplated copper layer.

8. The integrated circuit structure of claim 1, wherein said coil is configured for an inductor.

9. The integrated circuit structure of claim 1, wherein said first product is smaller than said second product by at least 1000 times.

10. The integrated circuit structure of claim 1, wherein said first product is smaller than said second product by at least 10,000 times.

40. The integrated circuit structure of claim 1, wherein said polymer layer has a top surface with a first region vertically under said coil and a second region vertically under said metal interconnect, wherein said first region is substantially coplanar with said second region.

11. An integrated circuit structure comprising:

a silicon substrate;

a transistor in and on said silicon substrate;

a first dielectric layer over said silicon substrate;

a metallization structure over said first dielectric layer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer;

a second dielectric layer over said first dielectric layer and between said first and second metal layers;

a metal trace over said silicon substrate;

a passivation layer over said metallization structure, said first and second dielectric layers and said metal trace, wherein a first opening in said passivation layer is over a contact point of said metallization structure, and said contact point is at a bottom of said first opening, wherein said passivation layer comprises a nitride;

a first polymer layer on said passivation layer, wherein said first polymer layer has a thickness between 2 and 150 micrometers, wherein a second opening in said first polymer layer is over said contact point;

a coil on said first polymer layer, wherein said coil comprises a glue layer, a gold seed layer having a thickness between 0.03 and 0.3 micrometer on said glue layer, and an electroplated gold layer having a thickness between 1 and 20 micrometers on said gold seed layer, wherein there is an undercut with an edge of said glue layer recessed from an edge of said electroplated gold layer, wherein a first product of resistance of a first section of said coil times capacitance of said first section is at least 100 times smaller than a second product of resistance of a second section of said metal trace times capacitance of said second section, wherein said first section has a same length as said second section; and

a metal interconnect on said first polymer layer and said contact point, wherein said metal interconnect is connected to said contact point through said second opening, wherein said metal interconnect is configured to be connected to a wirebond.

12. The integrated circuit structure of claim 11, wherein said first polymer layer comprises polyimide.

13. The integrated circuit structure of claim 11, wherein said first polymer layer comprises benzocyclobutene (BCB).

14. The integrated circuit structure of claim 11 further comprising a second polymer layer over said coil, said metal interconnect and said first polymer layer.

15. The integrated circuit structure of claim 11, wherein said coil is configured for an inductor.

16. The integrated circuit structure of claim 11, wherein said glue layer comprises titanium.

17. The integrated circuit structure of claim 11, wherein said glue layer comprises tungsten.

18. The integrated circuit structure of claim 11, wherein said glue layer has a thickness between 0.05 and 0.5 micrometers.

19. The integrated circuit structure of claim 11, wherein said first product is smaller than said second product by at least 1000 times.

20. The integrated circuit structure of claim 11, wherein said first product is smaller than said second product by at least 10,000 times.

21. An integrated circuit structure comprising:

a silicon substrate;

a first dielectric layer over said silicon substrate;

a metallization structure over said first dielectric layer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer;

a second dielectric layer over said first dielectric layer and between said first and second metal layers;

a metal trace over said silicon substrate;

a separating layer over said metallization structure, said first and second dielectric layers and said metal trace, wherein an opening in said separating layer is over a contact point of said metallization structure, and said contact point is at a bottom of said opening; and

a coil over said separating layer, wherein there is no polymer layer between said coil and said separating layer, wherein a first product of resistance of a first section of said coil times capacitance of said first section is at least 1,000 times smaller than a second product of resistance of a second section of said metal trace times capacitance of said second section, wherein said first section has a same length as said second section.

22. The integrated circuit structure of claim 21, wherein said separating layer comprises an oxide.

23. The integrated circuit structure of claim 21, wherein said separating layer comprises a nitride.

24. The integrated circuit structure of claim 21, wherein said metal trace comprises aluminum.

25. The integrated circuit structure of claim 21, wherein said metal trace comprises copper.

26. The integrated circuit structure of claim 21, wherein said first product is smaller than said second product by at least 10,000 times.

27. The integrated circuit structure of claim 21, wherein said coil comprises electroplated copper.

28. An integrated circuit structure comprising:

a silicon substrate;

a first dielectric layer over said silicon substrate;

a metallization structure over said first dielectric layer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer;

a second dielectric layer over said first dielectric layer and between said first and second metal layers;

a metal trace over said silicon substrate;

a separating layer over said metallization structure, said first and second dielectric layers and said metal trace, wherein an opening in said separating layer is over a contact point of said metallization structure, and said contact point is at a bottom of said opening; and

a metal interconnect over said separating layer, wherein there is no polymer layer between said metal interconnect and said separating layer, wherein a first product of resistance of a first section of said metal interconnect times capacitance of said first section is at least 1,000 times smaller than a second product of resistance of a second section of said metal trace times capacitance of said second section, wherein said first section has a same length as said second section.

29. The integrated circuit structure of claim 28, wherein said separating layer comprises an oxide.

30. The integrated circuit structure of claim 28, wherein said separating layer comprises a nitride.

31. The integrated circuit structure of claim 28, wherein said metal trace comprises aluminum.

32. The integrated circuit structure of claim 28, wherein said metal trace comprises copper.

33. The integrated circuit structure of claim 28, wherein said first product is smaller than said second product by at least 10,000 times.

34. The integrated circuit structure of claim 28, wherein said metal interconnect comprises electroplated copper.

35. An integrated circuit structure comprising:

a silicon substrate;

a first dielectric layer over said silicon substrate;

a metallization structure over said first dielectric layer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer;

a second dielectric layer over said first dielectric layer and between said first and second metal layers;

a metal trace over said silicon substrate;

a separating layer over said metallization structure, said first and second dielectric layers and said metal trace, wherein an opening in said separating layer is over a contact point of said metallization structure, and said contact point is at a bottom of said opening;

a polymer layer over said separating layer; and

a metal interconnect over said polymer layer, wherein a first product of resistance of a first section of said metal interconnect times capacitance of said first section is at least 10,000 times smaller than a second product of resistance of a second section of said metal trace times capacitance of said second section, wherein said first section has a same length as said second section.

36. The integrated circuit structure of claim 35, wherein said separating layer comprises an oxide.

37. The integrated circuit structure of claim 35, wherein said separating layer comprises a nitride.

38. The integrated circuit structure of claim 35, wherein said metal trace comprises aluminum.

39. The integrated circuit structure of claim 35, wherein said metal trace comprises copper.