Post passivation interconnection process and structures
First Claim
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1. An integrated circuit structure comprising:
- a silicon substrate;
a transistor in and on said silicon substrate;
a first dielectric layer over said silicon substrate;
a metallization structure over said first dielectric layer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer;
a second dielectric layer over said first dielectric layer and between said first and second metal layers;
a metal trace over said silicon substrate;
a contact pad over said silicon substrate;
a passivation layer over said metallization structure, said first and second dielectric layers and said metal trace, wherein a first opening in said passivation layer is over a contact point of said contact pad, and said contact point is at a bottom of said first opening, wherein said passivation layer comprises a nitride;
a polymer layer on a top surface of said passivation layer, wherein said polymer layer has a thickness between 2 and 150 micrometers, wherein a second opening in said polymer layer is over said contact point and over a region of said top surface of said passivation layer;
a coil on said polymer layer, wherein said coil comprises a glue layer, a copper seed layer having a thickness between 0.2 and 1 micrometer on said glue layer, and an electroplated copper layer having a thickness between 3 and 20 micrometers on said copper seed layer, wherein there is an undercut with an edge of said glue layer recessed from an edge of said electroplated copper layer, wherein a first product of resistance of a first section of said coil times capacitance of said first section is at least 100 times smaller than a second product of resistance of a second section of said metal trace times capacitance of said second section, wherein said first section has a same length as said second section;
a metal interconnect on said polymer layer, said region of said top surface of said passivation layer, and said contact point, wherein said metal interconnect is connected to said contact point through said first and second openings; and
a solder bump connected to said metal interconnect.
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Abstract
A system and method for forming post passivation metal structures is described. Metal interconnections and high quality electrical components, such as inductors, transformers, capacitors, or resistors are formed on a layer of passivation, or on a thick layer of polymer over a passivation layer.
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Citations
40 Claims
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1. An integrated circuit structure comprising:
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a silicon substrate; a transistor in and on said silicon substrate; a first dielectric layer over said silicon substrate; a metallization structure over said first dielectric layer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer; a second dielectric layer over said first dielectric layer and between said first and second metal layers; a metal trace over said silicon substrate; a contact pad over said silicon substrate; a passivation layer over said metallization structure, said first and second dielectric layers and said metal trace, wherein a first opening in said passivation layer is over a contact point of said contact pad, and said contact point is at a bottom of said first opening, wherein said passivation layer comprises a nitride; a polymer layer on a top surface of said passivation layer, wherein said polymer layer has a thickness between 2 and 150 micrometers, wherein a second opening in said polymer layer is over said contact point and over a region of said top surface of said passivation layer; a coil on said polymer layer, wherein said coil comprises a glue layer, a copper seed layer having a thickness between 0.2 and 1 micrometer on said glue layer, and an electroplated copper layer having a thickness between 3 and 20 micrometers on said copper seed layer, wherein there is an undercut with an edge of said glue layer recessed from an edge of said electroplated copper layer, wherein a first product of resistance of a first section of said coil times capacitance of said first section is at least 100 times smaller than a second product of resistance of a second section of said metal trace times capacitance of said second section, wherein said first section has a same length as said second section; a metal interconnect on said polymer layer, said region of said top surface of said passivation layer, and said contact point, wherein said metal interconnect is connected to said contact point through said first and second openings; and a solder bump connected to said metal interconnect. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 40)
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11. An integrated circuit structure comprising:
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a silicon substrate; a transistor in and on said silicon substrate; a first dielectric layer over said silicon substrate; a metallization structure over said first dielectric layer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer; a second dielectric layer over said first dielectric layer and between said first and second metal layers; a metal trace over said silicon substrate; a passivation layer over said metallization structure, said first and second dielectric layers and said metal trace, wherein a first opening in said passivation layer is over a contact point of said metallization structure, and said contact point is at a bottom of said first opening, wherein said passivation layer comprises a nitride; a first polymer layer on said passivation layer, wherein said first polymer layer has a thickness between 2 and 150 micrometers, wherein a second opening in said first polymer layer is over said contact point; a coil on said first polymer layer, wherein said coil comprises a glue layer, a gold seed layer having a thickness between 0.03 and 0.3 micrometer on said glue layer, and an electroplated gold layer having a thickness between 1 and 20 micrometers on said gold seed layer, wherein there is an undercut with an edge of said glue layer recessed from an edge of said electroplated gold layer, wherein a first product of resistance of a first section of said coil times capacitance of said first section is at least 100 times smaller than a second product of resistance of a second section of said metal trace times capacitance of said second section, wherein said first section has a same length as said second section; and a metal interconnect on said first polymer layer and said contact point, wherein said metal interconnect is connected to said contact point through said second opening, wherein said metal interconnect is configured to be connected to a wirebond. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. An integrated circuit structure comprising:
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a silicon substrate; a first dielectric layer over said silicon substrate; a metallization structure over said first dielectric layer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer; a second dielectric layer over said first dielectric layer and between said first and second metal layers; a metal trace over said silicon substrate; a separating layer over said metallization structure, said first and second dielectric layers and said metal trace, wherein an opening in said separating layer is over a contact point of said metallization structure, and said contact point is at a bottom of said opening; and a coil over said separating layer, wherein there is no polymer layer between said coil and said separating layer, wherein a first product of resistance of a first section of said coil times capacitance of said first section is at least 1,000 times smaller than a second product of resistance of a second section of said metal trace times capacitance of said second section, wherein said first section has a same length as said second section. - View Dependent Claims (22, 23, 24, 25, 26, 27)
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28. An integrated circuit structure comprising:
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a silicon substrate; a first dielectric layer over said silicon substrate; a metallization structure over said first dielectric layer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer; a second dielectric layer over said first dielectric layer and between said first and second metal layers; a metal trace over said silicon substrate; a separating layer over said metallization structure, said first and second dielectric layers and said metal trace, wherein an opening in said separating layer is over a contact point of said metallization structure, and said contact point is at a bottom of said opening; and a metal interconnect over said separating layer, wherein there is no polymer layer between said metal interconnect and said separating layer, wherein a first product of resistance of a first section of said metal interconnect times capacitance of said first section is at least 1,000 times smaller than a second product of resistance of a second section of said metal trace times capacitance of said second section, wherein said first section has a same length as said second section. - View Dependent Claims (29, 30, 31, 32, 33, 34)
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35. An integrated circuit structure comprising:
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a silicon substrate; a first dielectric layer over said silicon substrate; a metallization structure over said first dielectric layer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer; a second dielectric layer over said first dielectric layer and between said first and second metal layers; a metal trace over said silicon substrate; a separating layer over said metallization structure, said first and second dielectric layers and said metal trace, wherein an opening in said separating layer is over a contact point of said metallization structure, and said contact point is at a bottom of said opening; a polymer layer over said separating layer; and a metal interconnect over said polymer layer, wherein a first product of resistance of a first section of said metal interconnect times capacitance of said first section is at least 10,000 times smaller than a second product of resistance of a second section of said metal trace times capacitance of said second section, wherein said first section has a same length as said second section. - View Dependent Claims (36, 37, 38, 39)
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Specification