Systems and apparatus with programmable memory control for heterogeneous main memory
First Claim
1. A main memory comprising:
- a programmable heterogeneous memory controller having a first memory channel interface to couple to a first memory channel;
the first memory channel coupled to the programmable heterogeneous memory controller, the first memory channel havinga first memory channel bus coupled to the first memory channel interface of the programmable heterogeneous memory controller, anda plurality of sockets coupled to the first memory channel bus, the plurality of sockets capable of respectively receiving a plurality of memory modules; and
wherein the programmable heterogeneous memory controller just prior to accessing a first memory module adapts the first memory channel interface on the fly to communicate with the first memory module with a first type of memory, just prior to accessing a second memory module adapts the first memory channel interface on the fly to communicate with the second memory module with a second type of memory differing from the first type of memory, and just prior to accessing a third memory module adapts the first memory channel interface on the fly to communicate with the third memory module with a third type of memory differing from the second type of memory.
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Accused Products
Abstract
A computer system is disclosed including a printed circuit board (PCB) including a plurality of traces, at least one processor mounted to the PCB to couple to some of the plurality of traces, a heterogeneous memory channel including a plurality of sockets coupled to a memory channel bus of the PCB, and a memory controller coupled between the at least one processor and the heterogeneous memory channel. The heterogeneous memory channel includes a plurality of sockets coupled to a memory channel bus of the PCB. The plurality of sockets are configured to receive a plurality of different types of memory modules. The memory controller may be a programmable heterogeneous memory controller to flexibly adapt to the memory channel bus to control access to each of the different types of memory modules in the heterogeneous memory channel.
166 Citations
43 Claims
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1. A main memory comprising:
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a programmable heterogeneous memory controller having a first memory channel interface to couple to a first memory channel; the first memory channel coupled to the programmable heterogeneous memory controller, the first memory channel having a first memory channel bus coupled to the first memory channel interface of the programmable heterogeneous memory controller, and a plurality of sockets coupled to the first memory channel bus, the plurality of sockets capable of respectively receiving a plurality of memory modules; and wherein the programmable heterogeneous memory controller just prior to accessing a first memory module adapts the first memory channel interface on the fly to communicate with the first memory module with a first type of memory, just prior to accessing a second memory module adapts the first memory channel interface on the fly to communicate with the second memory module with a second type of memory differing from the first type of memory, and just prior to accessing a third memory module adapts the first memory channel interface on the fly to communicate with the third memory module with a third type of memory differing from the second type of memory. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23)
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24. A main memory comprising:
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a memory controller having one or more memory channel interfaces to couple to one or more respective memory channels; a memory channel having a memory channel bus coupled to one memory channel interface of the memory controller; a first dynamic random access memory module coupled to the memory channel bus; and a first non-volatile memory module coupled to the memory channel bus; wherein communication over the memory channel bus is specified by a standard specification with standard specification data and instructions, and wherein the first non-volatile memory module is a translating memory module, the translating memory module including a printed circuit board; a non-volatile memory integrated circuit mounted to the printed circuit board; and a translator mounted to the printed circuit board and coupled between the memory channel bus and the non-volatile memory integrated circuit, the translator configured to translate standard specification data and instructions read from the memory channel bus into memory data and instructions for the non-volatile memory integrated circuit, the translator further configured to translate data and instructions from the non-volatile memory integrated circuit into standard specification data and instructions for writing out to the memory channel bus. - View Dependent Claims (25, 26)
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27. A computer system comprising:
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a printed circuit board including a plurality of traces; at least one processor coupled to one or more of the plurality of traces of the printed circuit board; a first heterogeneous memory channel including a first plurality of sockets coupled to a first memory channel bus of the printed circuit board, the first plurality of sockets to receive printed circuit boards of a first plurality of different types of memory modules; a programmable heterogeneous memory controller coupled between the at least one processor and the first heterogeneous memory channel, the programmable heterogeneous memory controller configured to control access to the first plurality of different types of memory modules in the first heterogeneous memory channel; and wherein just prior to accessing a first memory module the programmable heterogeneous memory controller flexibly adapts the first memory channel bus on the fly to control access to a first type of memory module in the first heterogeneous memory channel, just prior to accessing a second memory module, the programmable heterogeneous memory controller flexibly adapts the first memory channel bus on the fly to control access to a second type of memory module in the first heterogeneous memory channel differing from the first type of memory module, and just prior to accessing a third memory module, the programmable heterogeneous memory controller flexibly adapts the first memory channel bus on the fly to control access to a third type of memory module in the first heterogeneous memory channel differing from the second type of memory module. - View Dependent Claims (28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39)
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40. A main memory comprising:
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a first plurality of memory module sockets to receive one or more first memory modules; a memory controller having a first memory channel interface to couple to the first plurality of memory module sockets and the one or more first memory modules received therein; a first memory channel bus coupled between the first memory channel interface of the memory controller and the first plurality of memory module sockets; a first plurality of independent point to point feedback status signals coupled between the memory controller and each respective memory module socket, the one or more first memory modules configured to respectively couple to the first plurality of independent point to point feedback status signals; and wherein each of the first plurality of independent point-to-point feedback status signals are communicated from each respective memory module to the memory controller to indicate to the memory controller a respective status of the respective memory module received in the respective memory module socket. - View Dependent Claims (41, 42, 43)
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Specification