Method of wire bonding over active area of a semiconductor circuit
First Claim
1. A method for fabricating a circuit component, comprising:
- providing a semiconductor substrate, an active device in or over said semiconductor substrate, a first interconnect metal layer over said semiconductor substrate, a dielectric layer over said first interconnect metal layer and said semiconductor substrate, a second interconnect metal layer over said dielectric layer, and a passivation layer over said active device, said dielectric layer and said first and second interconnect metal layers, wherein a first opening in said passivation layer is over a contact point of said second interconnect metal layer, and said contact point is at a bottom of said first opening;
forming a metal pad over said semiconductor substrate, wherein said metal pad is connected to said contact point through said first opening, wherein said forming said metal pad comprises forming a glue layer on said contact point and over said passivation layer, followed by forming a seed layer on said glue layer, followed by forming a photoresist layer on said seed layer, wherein a second opening in said photoresist layer exposes a region of said seed layer, followed by electroplating a copper layer on said region, wherein said copper layer has a thickness greater than 1 micrometer, followed by electroplating a nickel layer on said copper layer in said second opening, wherein said nickel layer has a thickness greater than 0.5 micrometers, followed by electroless plating a gold layer on said nickel layer in said second opening, followed by removing said photoresist layer, followed by etching said seed layer and said glue layer; and
bonding a wire to said metal pad using a wirebonding process, wherein a contact area between said metal pad and said wire is vertically over said active device.
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Accused Products
Abstract
A method and structure are provided to enable wire bond connections over active and/or passive devices and/or low-k dielectrics, formed on an Integrated Circuit die. A semiconductor substrate having active and/or passive devices is provided, with interconnect metallization formed over the active and/or passive devices. A passivation layer formed over the interconnect metallization is provided, wherein openings are formed in the passivation layer to an upper metal layer of the interconnect metallization. Compliant metal bond pads are formed over the passivation layer, wherein the compliant metal bond pads are connected through the openings to the upper metal layer, and wherein the compliant metal bond pads are formed substantially over the active and/or passive devices. The compliant metal bond pads may be formed of a composite metal structure.
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Citations
38 Claims
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1. A method for fabricating a circuit component, comprising:
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providing a semiconductor substrate, an active device in or over said semiconductor substrate, a first interconnect metal layer over said semiconductor substrate, a dielectric layer over said first interconnect metal layer and said semiconductor substrate, a second interconnect metal layer over said dielectric layer, and a passivation layer over said active device, said dielectric layer and said first and second interconnect metal layers, wherein a first opening in said passivation layer is over a contact point of said second interconnect metal layer, and said contact point is at a bottom of said first opening; forming a metal pad over said semiconductor substrate, wherein said metal pad is connected to said contact point through said first opening, wherein said forming said metal pad comprises forming a glue layer on said contact point and over said passivation layer, followed by forming a seed layer on said glue layer, followed by forming a photoresist layer on said seed layer, wherein a second opening in said photoresist layer exposes a region of said seed layer, followed by electroplating a copper layer on said region, wherein said copper layer has a thickness greater than 1 micrometer, followed by electroplating a nickel layer on said copper layer in said second opening, wherein said nickel layer has a thickness greater than 0.5 micrometers, followed by electroless plating a gold layer on said nickel layer in said second opening, followed by removing said photoresist layer, followed by etching said seed layer and said glue layer; and bonding a wire to said metal pad using a wirebonding process, wherein a contact area between said metal pad and said wire is vertically over said active device. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method for fabricating a circuit component, comprising:
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providing a semiconductor substrate, an active device in or over said semiconductor substrate, a first interconnect metal layer over said semiconductor substrate, a dielectric layer over said first interconnect metal layer and said semiconductor substrate, a second interconnect metal layer over said dielectric layer, a passivation layer over said active device, said dielectric layer and said first and second interconnect metal layers, wherein a first opening in said passivation layer is over a contact point of said second interconnect metal layer, and said contact point is at a bottom of said first opening, and a polymer layer on said passivation layer, wherein a second opening in said polymer layer is over said contact point; forming a metal pad over said polymer layer, wherein said metal pad is connected to said contact point through said second opening, wherein said forming said metal pad comprises forming a glue layer, forming a seed layer on said glue layer, forming a photoresist layer on said seed layer, wherein a third opening in said photoresist layer exposes a region of said seed layer, electroplating a copper layer on said region, wherein said copper layer has a thickness greater than 1 micrometer, forming a nickel layer on said copper layer, electroless plating a gold layer on said nickel layer, removing said photoresist layer, and etching said seed layer and said glue layer; and bonding a wire to said metal pad using a wirebonding process, wherein a contact area between said metal pad and said wire is vertically over said active device. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. A method for fabricating a circuit component, comprising:
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providing a semiconductor substrate, an active device in or over said semiconductor substrate, a first interconnect metal layer over said semiconductor substrate, a dielectric layer over said first interconnect metal layer and said semiconductor substrate, a second interconnect metal layer over said dielectric layer, a passivation layer over said active device, said dielectric layer and said first and second interconnect metal layers, wherein a first opening in said passivation layer is over a contact point of said second interconnect metal layer, and said contact point is at a bottom of said first opening, wherein said passivation layer comprises a nitride layer, and a polymer layer on said passivation layer, wherein a second opening in said polymer layer is over said contact point; forming a metal pad over said polymer layer, wherein said metal pad is connected to said contact point through said second opening, wherein said forming said metal pad comprises forming a glue layer, followed by forming a first copper layer on said glue layer, followed by electroplating a second copper layer on said first copper layer, wherein said second copper layer has a thickness greater than 1 micrometer, followed by forming a nickel layer on said second copper layer, followed by forming a gold layer over said nickel layer; and bonding a wire to said metal pad using a wirebonding process, wherein a contact area between said metal pad and said wire is vertically over said active device and not vertically over said contact point. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28)
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29. A method for fabricating a circuit component, comprising:
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providing a semiconductor substrate, an active device in or over said semiconductor substrate, a first dielectric layer over said semiconductor substrate, a first metal interconnect over said first dielectric layer, a second dielectric layer over said first metal interconnect and said first dielectric layer, a second metal interconnect on said second dielectric layer, a third metal interconnect on said second dielectric layer, wherein said second and third metal interconnects are at a same horizontal level, wherein said second metal interconnect has a portion spaced apart from said third metal interconnect, and a passivation layer over said second dielectric layer and on said third metal interconnect, wherein a first opening in said passivation layer is over a contact point of said second metal interconnect, and said contact point is at a bottom of said first opening, wherein said passivation layer comprises a nitride; forming a metal pad over said semiconductor substrate, wherein said metal pad is connected to said contact point through said first opening, wherein said forming said metal pad comprises forming a glue layer on said contact point and over said passivation layer, followed by forming a first copper layer on said glue layer, followed by forming a photoresist layer on said first copper layer, wherein a second opening in said photoresist layer exposes a region of said first copper layer, followed by electroplating a second copper layer on said region, wherein said second copper layer has a thickness greater than 1 micrometer, followed by electroplating a nickel layer on said second copper layer in said second opening, followed by forming a wirebondable layer over said nickel layer in said second opening, followed by removing said photoresist layer, followed by etching said first copper layer and said glue layer; and bonding a wire to said metal pad using a wirebonding process, wherein a contact area between said wire and said metal pad is vertically over said active device, vertically over said third metal interconnect, vertically over a first sidewall of said third metal interconnect and vertically over a second sidewall of said third metal interconnect, wherein said first sidewall is opposite to said second sidewall. - View Dependent Claims (30, 31, 32, 33, 34)
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35. A method for fabricating a circuit component, comprising:
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providing a semiconductor substrate, an active device in or over said semiconductor substrate, a first dielectric layer over said semiconductor substrate, a first metal interconnect over said first dielectric layer, a second dielectric layer over said first metal interconnect and said first dielectric layer, a second metal interconnect on said second dielectric layer, a third metal interconnect on said second dielectric layer, wherein said second and third metal interconnects are at a same horizontal level, wherein said second metal interconnect has a portion spaced apart from said third metal interconnect, a passivation layer over said second dielectric layer and on said third metal interconnect, wherein an opening in said passivation layer is over a contact point of said second metal interconnect, and said contact point is at a bottom of said opening, wherein said passivation layer comprises a nitride, a polymer layer over said passivation layer, and a metal pad over said passivation layer, wherein said metal pad is connected to said contact point through said opening, wherein said metal pad comprises a glue layer, a first copper layer on said glue layer, a second copper layer on said first copper layer, a nickel layer on said second copper layer and a wirebondable layer over said nickel layer; and bonding a wire to said metal pad using a wirebonding process, wherein a contact area between said wire and said metal pad is vertically over said active device, vertically over said third metal interconnect, vertically over a first sidewall of said third metal interconnect and vertically over a second sidewall of said third metal interconnect, wherein said first sidewall is opposite to said second sidewall. - View Dependent Claims (36, 37, 38)
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Specification