Method of wire bonding over active area of a semiconductor circuit

• US 8,138,079 B2
• Filed: 10/29/2007
• Issued: 03/20/2012
• Est. Priority Date: 12/21/1998
• Status: Expired due to Term

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lee, Jin-Yuan, Chen, Ying-Chih, Lin, Mou-Shiung
• Primary Examiner(s): PIZARRO CRESPO, MARCOS D
• Application Number:
  US11/926,154
• Publication Number:
  US 20080233733A1
• Time in Patent Office: 1,604 Days
• Field of Search: 257/E21.158, 257/E21.506, 257/E21.575, 438612-618, 438622-625, 438/627, 438/628, 438/637, 438642-644, 438/648, 438/650
• US Class Current: 438/614
• CPC Class Codes: H01L 2224/02166 Collar structures
• CPC Class Codes: H01L 2224/023 Redistribution layers [RDL] for bonding areas
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05073 Single internal layer
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05171 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/05187 Ceramics, e.g. crystalline carbides, nitrides or oxides glass ceramics H01L2224/05188
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05556 in side view
• CPC Class Codes: H01L 2224/05558 conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/4807 of bonding interfaces, e.g. interlocking features
• CPC Class Codes: H01L 2224/48453 of the interface with the bonding area
• CPC Class Codes: H01L 2224/48463 the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 2224/48599 Principal constituent of the connecting portion of the wire connector being Gold (Au)
• CPC Class Codes: H01L 2224/48624 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48644 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48647 : Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/854 : with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
• CPC Class Codes: H01L 2224/85424 : Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/85444 : Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/85447 : Copper (Cu) as principal constituent
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01007 : Nitrogen [N]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor

Abstract

A method and structure are provided to enable wire bond connections over active and/or passive devices and/or low-k dielectrics, formed on an Integrated Circuit die. A semiconductor substrate having active and/or passive devices is provided, with interconnect metallization formed over the active and/or passive devices. A passivation layer formed over the interconnect metallization is provided, wherein openings are formed in the passivation layer to an upper metal layer of the interconnect metallization. Compliant metal bond pads are formed over the passivation layer, wherein the compliant metal bond pads are connected through the openings to the upper metal layer, and wherein the compliant metal bond pads are formed substantially over the active and/or passive devices. The compliant metal bond pads may be formed of a composite metal structure.

Claims

1. A method for fabricating a circuit component, comprising:

providing a semiconductor substrate, an active device in or over said semiconductor substrate, a first interconnect metal layer over said semiconductor substrate, a dielectric layer over said first interconnect metal layer and said semiconductor substrate, a second interconnect metal layer over said dielectric layer, and a passivation layer over said active device, said dielectric layer and said first and second interconnect metal layers, wherein a first opening in said passivation layer is over a contact point of said second interconnect metal layer, and said contact point is at a bottom of said first opening;

forming a metal pad over said semiconductor substrate, wherein said metal pad is connected to said contact point through said first opening, wherein said forming said metal pad comprises forming a glue layer on said contact point and over said passivation layer, followed by forming a seed layer on said glue layer, followed by forming a photoresist layer on said seed layer, wherein a second opening in said photoresist layer exposes a region of said seed layer, followed by electroplating a copper layer on said region, wherein said copper layer has a thickness greater than 1 micrometer, followed by electroplating a nickel layer on said copper layer in said second opening, wherein said nickel layer has a thickness greater than 0.5 micrometers, followed by electroless plating a gold layer on said nickel layer in said second opening, followed by removing said photoresist layer, followed by etching said seed layer and said glue layer; and

bonding a wire to said metal pad using a wirebonding process, wherein a contact area between said metal pad and said wire is vertically over said active device.

2. The method of claim 1 further comprising forming a polymer layer on said passivation layer, followed by said forming said metal pad further on said polymer layer.

3. The method of claim 1, wherein said forming said glue layer comprises sputtering a titanium-containing layer on said contact point and over said passivation layer.

4. The method of claim 1, wherein said forming said glue layer comprises sputtering a chromium-containing layer on said contact point and over said passivation layer.

5. The method of claim 1, wherein said gold layer has a thickness greater than 0.1 micrometers.

6. The method of claim 1, wherein said contact area has a width greater than that of said first opening.

7. The method of claim 1, wherein said forming said seed layer comprises a sputtering process.

8. The method of claim 1, wherein said passivation layer comprises a nitride layer.

9. The method of claim 1, wherein said forming said seed layer comprises forming a copper seed layer on said glue layer.

10. A method for fabricating a circuit component, comprising:

providing a semiconductor substrate, an active device in or over said semiconductor substrate, a first interconnect metal layer over said semiconductor substrate, a dielectric layer over said first interconnect metal layer and said semiconductor substrate, a second interconnect metal layer over said dielectric layer, a passivation layer over said active device, said dielectric layer and said first and second interconnect metal layers, wherein a first opening in said passivation layer is over a contact point of said second interconnect metal layer, and said contact point is at a bottom of said first opening, and a polymer layer on said passivation layer, wherein a second opening in said polymer layer is over said contact point;

forming a metal pad over said polymer layer, wherein said metal pad is connected to said contact point through said second opening, wherein said forming said metal pad comprises forming a glue layer, forming a seed layer on said glue layer, forming a photoresist layer on said seed layer, wherein a third opening in said photoresist layer exposes a region of said seed layer, electroplating a copper layer on said region, wherein said copper layer has a thickness greater than 1 micrometer, forming a nickel layer on said copper layer, electroless plating a gold layer on said nickel layer, removing said photoresist layer, and etching said seed layer and said glue layer; and

bonding a wire to said metal pad using a wirebonding process, wherein a contact area between said metal pad and said wire is vertically over said active device.

11. The method of claim 10, wherein said passivation layer comprises a nitride layer.

12. The method of claim 10, wherein said providing said polymer layer comprises forming a polyimide layer on said passivation layer.

13. The method of claim 10, wherein said gold layer has a thickness greater than 0.1 micrometers.

14. The method of claim 10, wherein said contact area has a width greater than that of said first opening.

15. The method of claim 10, wherein said forming said seed layer comprises a sputtering process.

16. The method of claim 10, wherein said providing said polymer layer comprises a spin-coating process.

17. The method of claim 10, wherein said forming said glue layer comprises sputtering a titanium-containing layer.

18. The method of claim 10, wherein said forming said glue layer comprises sputtering a chromium-containing layer.

19. The method of claim 10, wherein said forming said seed layer comprises forming a copper seed layer on said glue layer.

20. The method of claim 10, wherein said forming said metal pad further comprises said forming said nickel layer with a thickness greater than 0.5 micrometers.

21. A method for fabricating a circuit component, comprising:

providing a semiconductor substrate, an active device in or over said semiconductor substrate, a first interconnect metal layer over said semiconductor substrate, a dielectric layer over said first interconnect metal layer and said semiconductor substrate, a second interconnect metal layer over said dielectric layer, a passivation layer over said active device, said dielectric layer and said first and second interconnect metal layers, wherein a first opening in said passivation layer is over a contact point of said second interconnect metal layer, and said contact point is at a bottom of said first opening, wherein said passivation layer comprises a nitride layer, and a polymer layer on said passivation layer, wherein a second opening in said polymer layer is over said contact point;

forming a metal pad over said polymer layer, wherein said metal pad is connected to said contact point through said second opening, wherein said forming said metal pad comprises forming a glue layer, followed by forming a first copper layer on said glue layer, followed by electroplating a second copper layer on said first copper layer, wherein said second copper layer has a thickness greater than 1 micrometer, followed by forming a nickel layer on said second copper layer, followed by forming a gold layer over said nickel layer; and

bonding a wire to said metal pad using a wirebonding process, wherein a contact area between said metal pad and said wire is vertically over said active device and not vertically over said contact point.

22. The method of claim 21, wherein said forming said glue layer comprises forming a titanium-containing layer.

23. The method of claim 21, wherein said contact area has a width greater than that of said first opening.

24. The method of claim 21, wherein said providing said polymer layer comprises a spin-coating process.

25. The method of claim 21, wherein said forming said glue layer comprises a sputtering process.

26. The method of claim 21, wherein said forming said first copper layer comprises a sputtering process.

27. The method of claim 21, wherein said forming said glue layer comprises sputtering a titanium-containing layer.

28. The method of claim 21, wherein said forming said metal pad further comprises said forming said nickel layer with a thickness greater than 0.5 micrometers.

29. A method for fabricating a circuit component, comprising:

providing a semiconductor substrate, an active device in or over said semiconductor substrate, a first dielectric layer over said semiconductor substrate, a first metal interconnect over said first dielectric layer, a second dielectric layer over said first metal interconnect and said first dielectric layer, a second metal interconnect on said second dielectric layer, a third metal interconnect on said second dielectric layer, wherein said second and third metal interconnects are at a same horizontal level, wherein said second metal interconnect has a portion spaced apart from said third metal interconnect, and a passivation layer over said second dielectric layer and on said third metal interconnect, wherein a first opening in said passivation layer is over a contact point of said second metal interconnect, and said contact point is at a bottom of said first opening, wherein said passivation layer comprises a nitride;

forming a metal pad over said semiconductor substrate, wherein said metal pad is connected to said contact point through said first opening, wherein said forming said metal pad comprises forming a glue layer on said contact point and over said passivation layer, followed by forming a first copper layer on said glue layer, followed by forming a photoresist layer on said first copper layer, wherein a second opening in said photoresist layer exposes a region of said first copper layer, followed by electroplating a second copper layer on said region, wherein said second copper layer has a thickness greater than 1 micrometer, followed by electroplating a nickel layer on said second copper layer in said second opening, followed by forming a wirebondable layer over said nickel layer in said second opening, followed by removing said photoresist layer, followed by etching said first copper layer and said glue layer; and

bonding a wire to said metal pad using a wirebonding process, wherein a contact area between said wire and said metal pad is vertically over said active device, vertically over said third metal interconnect, vertically over a first sidewall of said third metal interconnect and vertically over a second sidewall of said third metal interconnect, wherein said first sidewall is opposite to said second sidewall.

30. The method of claim 29, wherein said forming said glue layer comprises forming a titanium-containing layer on said contact point and over said passivation layer.

31. The method of claim 29, wherein said forming said wirebondable layer comprises electroplating a gold layer on said nickel layer.

32. The method of claim 29, wherein said forming said wirebondable layer comprises an electroplating process.

33. The method of claim 29, wherein said forming said wirebondable layer comprises an electroless plating process.

34. The method of claim 29, wherein said portion of said second metal interconnect comprises said contact point.

35. A method for fabricating a circuit component, comprising:

providing a semiconductor substrate, an active device in or over said semiconductor substrate, a first dielectric layer over said semiconductor substrate, a first metal interconnect over said first dielectric layer, a second dielectric layer over said first metal interconnect and said first dielectric layer, a second metal interconnect on said second dielectric layer, a third metal interconnect on said second dielectric layer, wherein said second and third metal interconnects are at a same horizontal level, wherein said second metal interconnect has a portion spaced apart from said third metal interconnect, a passivation layer over said second dielectric layer and on said third metal interconnect, wherein an opening in said passivation layer is over a contact point of said second metal interconnect, and said contact point is at a bottom of said opening, wherein said passivation layer comprises a nitride, a polymer layer over said passivation layer, and a metal pad over said passivation layer, wherein said metal pad is connected to said contact point through said opening, wherein said metal pad comprises a glue layer, a first copper layer on said glue layer, a second copper layer on said first copper layer, a nickel layer on said second copper layer and a wirebondable layer over said nickel layer; and

bonding a wire to said metal pad using a wirebonding process, wherein a contact area between said wire and said metal pad is vertically over said active device, vertically over said third metal interconnect, vertically over a first sidewall of said third metal interconnect and vertically over a second sidewall of said third metal interconnect, wherein said first sidewall is opposite to said second sidewall.

36. The method of claim 35, wherein said glue layer comprises a titanium-containing layer under said first copper layer.

37. The method of claim 35, wherein said wirebondable layer comprises a gold layer on said nickel layer.

38. The method of claim 35, wherein said portion of said second metal interconnect comprises said contact point.