Reading method, responder, and interrogator

• US 8,174,368 B2
• Filed: 02/12/2009
• Issued: 05/08/2012
• Est. Priority Date: 08/11/2003
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Usami, Mitsuo
• Primary Examiner(s): Wu, Daniel
• Assistant Examiner(s): GIRMA, FEKADESELASS
• Application Number:
  US12/370,263
• Publication Number:
  US 20090146794A1
• Time in Patent Office: 1,181 Days
• Field of Search: None
• US Class Current: 340/10.4
• CPC Class Codes: G06K 19/0723 the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs
• CPC Class Codes: G06K 7/0008 General problems related to the reading of electronic memory record carriers, independent of its reading method, e.g. power transfer
• CPC Class Codes: G06K 7/10039 interrogator driven, i.e. synchronous

Abstract

Transmission and reception of the identification number to/from an interrogator includes an interrogator that reads a recognition number from a responder by radio. When a clock pulse is modulated on a high-frequency carrier and transmitted to the responder from the antenna of the interrogator, there are a first case when the clock pulse interval is short and a second case when the clock pulse interval is long. By combining the clock pulse of the first case and the clock pulse of the second case so as to control the read of the recognition number from the interrogator, it is possible to realize reduction of the semiconductor chip size of the responder and suppress the cost of the semiconductor chip.

Claims

1. A responder comprising:

a memory cell holds an identification number;

a first counter with a first initial value;

a second counter with a second initial value different from the first initial value; and

an operation switching flip-flop;

wherein the second counter starts to count up a plurality of second clock pulses from the second initial value and the memory cell reads out each bit of the identification number according to a count value of the second counter after the first counter counts up a plurality of first clock pulses from the first initial value to a predetermined value, intervals of the plurality of first clock pulses and the plurality of second clock pulses being different from each other.

2. The responder according to claim 1, further comprising:

a decoder;

wherein the decoder decodes count values of the second counter and outputs decoder outputs to the memory cell, and

the memory cell outputs each bit of the identification number selected by the decoder outputs.

3. The responder according to claim 1, further comprising:

a selector unit;

a first page number setting unit which holds a first page number; and

a second page number setting unit which holds a second page number;

wherein the selector unit sets either one of the first page number and the second page number to the first counter as the initial number.

4. The responder according to claim 1,

wherein the intervals of the first clock pulses are longer than the intervals of the second clock pulses.

5. The responder according to claim 1,

wherein the responder receives the plurality of first clock pulses and the plurality of second clock pulses modulated by ASK modulation.

6. A responder comprising:

a memory cell holds an identification number;

a counter; and

an operation switching flip-flop;

wherein a plurality of first clock pulses are inputted into the counter when the operation switching flip-flop is in a set state,

a plurality of second clock pulses are inputted into the counter when the operation switching flip-flop is in a reset state,

the counter counts up the plurality of first clock pulses from a first initial value until a count value of the counter become zero,

after the count value of the counter become zero, the counter outputs a carry and the carry sets the operation switching flip-flop into the reset state, and

after the counter is set into the reset state, the counter starts to count up the plurality of second clock pulses from a second initial value different from the first initial value and the memory cell reads out each bit of the identification number according to a count value of the counter, intervals of the plurality of first clock pulses and the plurality of second clock pulses being different from each other.

7. The responder according to claim 6,

wherein the operation switching flip-flop outputs a first signal at a first level when the operation switching flip-flop is set in the set state;

and

the operation switching flip-flop outputs a second signal at a second level when the operation switching flip-flop is in the reset state.

8. The responder according to claim 6, further comprising:

a decoder;

wherein the decoder decodes count values of the counter and outputs decoder outputs to the memory cell; and

the memory cell outputs each bit of the identification number selected by the decoder outputs.

9. The responder according to claim 6, further comprising:

a selector unit;

a first page number setting unit which holds a first page number; and

a second page number setting unit which holds a second page number,

wherein the first selector unit sets either one of the first page number and the second page number to the first counter as the initial number.

10. The responder according to claim 6,

wherein the intervals of the plurality of first clock pulses are longer than the intervals of the plurality of second clock pulses.

11. The responder according to claim 6,

wherein the responder receives the plurality of first clock pulses and the plurality of second clock pulses modulated by ASK modulation.

12. A responder comprising:

a memory cell for holding an identification number having been assigned to the responder;

a pair of first and second counters, each of which has an initial value different from each other, for counting up the initial value to a predetermined value in response to either one of a first clock pulse or a second clock pulse sent from an interrogator connected to the responder;

wherein the first counter starts to count up a plurality of the first clock pulses, so that data including the identification number is transmitted from the responder to the interrogator according to a count value of the first counter with the predetermined value after the first counter counts up a plurality of first clock pulses from an initial value to another predetermined value, an interval of the first clock pulse being longer than an interval of the second clock pulse.

13. The responder according to claim 12, further comprising an operation switching flip-flop, wherein the data including the identification number is arranged to be transmitted when the operation switching flip-flop is set.

14. The responder according to claim 12, wherein the initial values for either one of the first or the second counters can be set in a plurality of times.

15. A responder comprising:

a memory cell for holding an identification number having been assigned to the responder;

a pair of first and second counters, each of which has an initial value arranged to be set in a plurality of times different from each other, for counting up the initial value to a predetermined value in response to either one of a first clock pulse or a second clock pulse sent from an interrogator connected to the responder; and

an operation switching flip-flop for outputting a setting signal, in response to a value of either one of the first or the second counters, by which the data including the identification number is transmitted;

wherein the first counter starts to count up the first clock pulse, so that the data is transmitted from the responder to the interrogator according to a count value of the first counter with the predetermined value after the first counter counts up a plurality of first clock pulses from an initial value to another predetermined value, an interval of the first clock pulse being longer than an interval of the second clock pulse.

16. An RFID system comprising an interrogator for outputting either one of first clock pulse or second clock pulse, an interval of the first clock pulse being longer than an interval of the second clock pulse;

and a plurality of responders, wherein the plurality of responders each include;

a memory cell for holding an identification number having been assigned to the responder;

a pair of first and second counters, each of which has an initial value arranged to be set in a plurality of times different from each other, for counting up the initial value to a predetermined value in response to either one of a first clock pulse or a second clock pulse sent from an interrogator connected to the responder; and

an operation switching flip-flop for outputting a setting signal, in response to a value of either one of the first or the second counters, by which the data including the identification number is transmitted;

wherein the first counter starts to count up the first clock pulse, so that the data is transmitted from the responder to the interrogator according to a count value of the first counter with the predetermined value after the first counter counts up a plurality of first clock pulses from an initial value to another predetermined value, the interval of the first clock pulse being longer than the interval of the second clock pulse.