Thin film transistor, method of manufacturing the same, and flat panel display having the same

• US 8,188,472 B2
• Filed: 01/07/2008
• Issued: 05/29/2012
• Est. Priority Date: 04/19/2007
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Park, Jae-chul, Kim, Chang-jung, Kim, Sun-il, Song, I-hun, Park, Young-soo
• Primary Examiner(s): Nguyen, Cuong Q
• Assistant Examiner(s): Gebreyesus, Yosef
• Application Number:
  US12/007,085
• Publication Number:
  US 20080258141A1
• Time in Patent Office: 1,604 Days
• Field of Search: 257/43, 257/59, 257/72, 257/83, 257/347, 257/348, 257/E29.117, 257/E29.273, 257/E29.289, 257/E29.137, 257/52, 257/57, 257/64, 257/66, 257/E29.003, 313/42, 313/498, 313/499, 313/500, 349/42, 349/43, 438/104
• US Class Current: 257/59
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A thin film transistor (TFT), a method of manufacturing the TFT, and a flat panel display comprising the TFT are provided. The TFT includes a gate, a gate insulating layer that contacts the gate, a channel layer that contacts the gate insulating layer and faces the gate with the gate insulating layer therebetween, a source that contacts an end of the channel layer; and a drain that contacts an other end of the channel layer, wherein the channel layer is an amorphous oxide semiconductor layer, and each of the source and the drain is a conductive oxide layer comprising an oxide semiconductor layer having a conductive impurity in the oxide semiconductor layer. A low resistance metal layer can further be included on the source and drain. A driving circuit of a unit pixel of a flat panel display includes the TFT.

Claims

1. A thin film transistor (TFT) comprising:

a gate;

a gate insulating layer contacting the gate;

a channel layer contacting the gate insulating layer on a side opposite the gate, the channel layer including an amorphous oxide semiconductor layer;

a source contacting a first end of the channel layer and consisting of a first conductive oxide layer;

a drain contacting a second end of the channel layer and consisting of a second conductive oxide layer;

a first low resistance metal layer on about the entire upper surface of the first conductive oxide layer; and

a second low resistance metal layer on about the entire upper surface of the second conductive oxide layer.

2. The TFT of claim 1, wherein the first and second conductive oxide layers have a basic composition identical to that of the amorphous oxide semiconductor layer of the channel layer.

3. The TFT of claim 2, wherein the channel layer is one layer selected from the group consisting of a ZnO layer, an IZO layer, and a G-I-Z-O layer.

4. The TFT of claim 1, wherein the first and second conductive oxide layers have a basic composition different from that of the amorphous oxide semiconductor layer of the channel layer.

5. The TFT of claim 4, wherein the channel layer is one layer selected from the group consisting of a ZnO layer, an IZO layer, and a G-I-Z-O layer.

6. The TFT of claim 1, wherein the channel layer is one layer selected from the group consisting of a ZnO layer, an IZO layer, and a G-I-Z-O layer.

7. The TFT of claim 1, wherein the first and second conductive oxide layers are formed from one layer selected from the group consisting of a G-I-Z-O layer, an ITO layer, an IZO layer, a ZnO layer, and a TiO layer.

8. The TFT of claim 1, wherein the first and second conductive oxide layers include a conductive impurity.

9. The TFT of claim 8, wherein the conductive impurity is one selected from the group consisting of Al, In, B, and Si.

10. The TFT of claim 1, wherein the first and second low resistance metal layers include a plurality of layers.

11. The TFT of claim 1, wherein the gate is one of above and below the channel layer.

12. The TFT of claim 1, further comprising an etch stopper on the channel layer between the source and the drain.

13. The TFT of claim 1, wherein the gate is one of a single layer and a plurality of layers.

14. The TFT of claim 13, wherein the gate includes a first MO layer, a gate metal layer, and a second Mo layer.

15. The TFT of claim 14, wherein the gate metal layer is an Al layer or an Nd layer.

16. A thin film transistor (TFT) comprising:

a gate;

a gate insulating layer on the gate;

a channel layer including an amorphous oxide semiconductor layer on the gate insulating layer, the gate insulating layer between the channel layer and the gate;

a source on a first end of the channel layer, the source consisting of a first conductive oxide layer and a first low resistance metal layer, the first low resistance metal layer covering the entire upper surface of the first conductive oxide layer; and

a drain on a second end of the channel layer, the drain consisting of a second conductive oxide layer and a second low resistance metal layer, the second low resistance metal layer covering the entire upper surface of the second conductive oxide layer.