Hardware task manager
First Claim
1. An integrated circuit comprising:
- a plurality of computing nodes;
a memory in at least one of the plurality of computing nodes, the plurality of computing nodes configured to make memory requests for access to the memory;
an interconnection network operatively coupled to the plurality of computing nodes, the interconnection network providing interconnections among the plurality of computing nodes to route the memory requests;
means for identifying a set of memory requests;
means for determining when all of the memory requests in the set of memory requests have been performed, wherein the means for determining when all of the memory requests in the set of memory requests have been performed is a ports counter; and
means for initiating execution of a task when all of the memory requests in the set of memory requests have been performed.
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Accused Products
Abstract
A hardware task manager for managing operations in an adaptive computing system. The task manager indicates when input and output buffer resources are sufficient to allow a task to execute. The task can require an arbitrary number of input values from one or more other (or the same) tasks. Likewise, a number of output buffers must also be available before the task can start to execute and store results in the output buffers. The hardware task manager maintains a counter in association with each input and output buffer. For input buffers, a negative value for the counter means that there is no data in the buffer and, hence, the respective input buffer is not ready or available. Thus, the associated task can not run. Predetermined numbers of bytes, or “units,” are stored into the input buffer and an associated counter is incremented. When the counter value transitions from a negative value to a zero the high-order bit of the counter is cleared, thereby indicating the input buffer has sufficient data and is available to be processed by a task.
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Citations
22 Claims
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1. An integrated circuit comprising:
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a plurality of computing nodes; a memory in at least one of the plurality of computing nodes, the plurality of computing nodes configured to make memory requests for access to the memory; an interconnection network operatively coupled to the plurality of computing nodes, the interconnection network providing interconnections among the plurality of computing nodes to route the memory requests; means for identifying a set of memory requests; means for determining when all of the memory requests in the set of memory requests have been performed, wherein the means for determining when all of the memory requests in the set of memory requests have been performed is a ports counter; and means for initiating execution of a task when all of the memory requests in the set of memory requests have been performed. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. An integrated circuit comprising:
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a plurality of computing nodes configured to make memory requests for access to a memory in at least one of the plurality of computing nodes; an interconnection network operatively coupled to the plurality of computing nodes, the interconnection network providing interconnections among the plurality of computing nodes to route the memory requests; and a task manager in the at least one of the computing nodes configured to identify a set of memory requests, determine when all of the memory requests in the set of memory requests have been performed and initiate execution of a task when all of the memory requests in the set of memory requests have been performed, wherein the task manager comprises a ports counter and a ready-to-run queue. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. A method for managing tasks within an integrated circuit having a plurality of computing nodes configured to make memory requests for access to a memory in at least one of the plurality of computing nodes, and an interconnection network operatively coupled to the plurality of computing nodes, the interconnection network providing interconnections among the plurality of computing nodes and the memory to route the memory requests, said method comprising:
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identifying a set of memory requests, wherein identifying a set of memory requests comprises identifying a port number and a task number for each memory request; determining when all of the memory requests in the set of memory requests have been performed; and initiating execution of a task when all of the memory requests in the set of memory requests have been performed. - View Dependent Claims (18, 19, 20, 21, 22)
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Specification