Multi-processor device with groups of processors consisting of respective separate external bus interfaces
First Claim
1. A multi-processor device comprising, over a single semiconductor chip:
- a plurality of processors including a plurality of a first type of processors and a plurality of a second type of processors, each said first type of processor having a first architecture, and each said second type of processor having a second architecture which is different from the first architecture of said first type of processor;
a first bus to which the plurality of the first type of processors is coupled;
a second bus to which the plurality of the second type of processors is coupled;
a first external bus interface to which the first bus is coupled;
a second external bus interface to which the second bus is coupled; and
a secondary cache over the single semiconductor chip that couples the first bus and the second bus to each other,wherein said first bus has a first maximum operating frequency, and said second bus has a second maximum operating frequency different from said first maximum operating frequency,wherein, in plan view, the first external bus interface is disposed at a first edge of the single semiconductor chip and the second external bus interface is disposed at a second edge of the single semiconductor chip different from said first edge,wherein said secondary cache is located between the first bus and the first external bus interface, or between the second bus and the second external bus interface, andwherein the plurality of the first type of processors and the plurality of the second type of processors are disposed separately in a layout region which includes the first bus and the plurality of the first type of processors and a layout region which includes the second bus and the plurality of the second type of processors, over the single semiconductor chip in plan view.
3 Assignments
0 Petitions
Accused Products
Abstract
The present invention intends to provide a high-performance multi-processor device in which independent buses and external bus interfaces are provided for each group of processors of different architectures, if a single chip includes a plurality of multi-processor groups. A multi-processor device of the present invention comprises a plurality of processors including first and second groups of processors of different architectures such as CPUs, SIMD type super-parallel processors, and DSPs, a first bus which is a CPU bus to which the first processor group is coupled, a second bus which is an internal peripheral bus to which the second processor group is coupled, independent of the first bus, a first external bus interface to which the first bus is coupled, and a second external bus interface to which the second bus is coupled, over a single semiconductor chip.
-
Citations
11 Claims
-
1. A multi-processor device comprising, over a single semiconductor chip:
-
a plurality of processors including a plurality of a first type of processors and a plurality of a second type of processors, each said first type of processor having a first architecture, and each said second type of processor having a second architecture which is different from the first architecture of said first type of processor; a first bus to which the plurality of the first type of processors is coupled; a second bus to which the plurality of the second type of processors is coupled; a first external bus interface to which the first bus is coupled; a second external bus interface to which the second bus is coupled; and a secondary cache over the single semiconductor chip that couples the first bus and the second bus to each other, wherein said first bus has a first maximum operating frequency, and said second bus has a second maximum operating frequency different from said first maximum operating frequency, wherein, in plan view, the first external bus interface is disposed at a first edge of the single semiconductor chip and the second external bus interface is disposed at a second edge of the single semiconductor chip different from said first edge, wherein said secondary cache is located between the first bus and the first external bus interface, or between the second bus and the second external bus interface, and wherein the plurality of the first type of processors and the plurality of the second type of processors are disposed separately in a layout region which includes the first bus and the plurality of the first type of processors and a layout region which includes the second bus and the plurality of the second type of processors, over the single semiconductor chip in plan view. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
-
Specification