Multi-processor device with groups of processors consisting of respective separate external bus interfaces

• US 8,200,878 B2
• Filed: 01/08/2008
• Issued: 06/12/2012
• Est. Priority Date: 01/22/2007
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Ishimi, Koichi
• Primary Examiner(s): Zaman, Faisal M
• Application Number:
  US11/970,732
• Publication Number:
  US 20080282012A1
• Time in Patent Office: 1,617 Days
• Field of Search: 710/306, 710/307, 710/313, 710/315, 712/29
• US Class Current: 710/306
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/3293 by switching to a less power-consuming processor, e.g. sub-CPU
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 13/4031 with arbitration
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 15/8007 single instruction multiple data [SIMD] multiprocessors
• CPC Class Codes: G06F 9/3887 controlled by a single instruction for multiple data lanes [SIMD]
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The present invention intends to provide a high-performance multi-processor device in which independent buses and external bus interfaces are provided for each group of processors of different architectures, if a single chip includes a plurality of multi-processor groups. A multi-processor device of the present invention comprises a plurality of processors including first and second groups of processors of different architectures such as CPUs, SIMD type super-parallel processors, and DSPs, a first bus which is a CPU bus to which the first processor group is coupled, a second bus which is an internal peripheral bus to which the second processor group is coupled, independent of the first bus, a first external bus interface to which the first bus is coupled, and a second external bus interface to which the second bus is coupled, over a single semiconductor chip.

Claims

1. A multi-processor device comprising, over a single semiconductor chip:

a plurality of processors including a plurality of a first type of processors and a plurality of a second type of processors, each said first type of processor having a first architecture, and each said second type of processor having a second architecture which is different from the first architecture of said first type of processor;

a first bus to which the plurality of the first type of processors is coupled;

a second bus to which the plurality of the second type of processors is coupled;

a first external bus interface to which the first bus is coupled;

a second external bus interface to which the second bus is coupled; and

a secondary cache over the single semiconductor chip that couples the first bus and the second bus to each other,

wherein said first bus has a first maximum operating frequency, and said second bus has a second maximum operating frequency different from said first maximum operating frequency,

wherein, in plan view, the first external bus interface is disposed at a first edge of the single semiconductor chip and the second external bus interface is disposed at a second edge of the single semiconductor chip different from said first edge,

wherein said secondary cache is located between the first bus and the first external bus interface, or between the second bus and the second external bus interface, and

wherein the plurality of the first type of processors and the plurality of the second type of processors are disposed separately in a layout region which includes the first bus and the plurality of the first type of processors and a layout region which includes the second bus and the plurality of the second type of processors, over the single semiconductor chip in plan view.

2. The multi-processor device according to claim 1, further comprising a bus bridge circuit that couples the first bus and the second bus.

3. The multi-processor device according to claim 1, wherein the first type of processor is a Central Processing Unit (CPU) and the second type of processor is a matrix type processor.

4. The multi-processor device according to claim 3, wherein a CPU of another architecture is also coupled to the bus to which the matrix type processors are coupled.

5. The multi-processor device according to claim 1, wherein the first type of processor is a Central Processing Unit (CPU) and the second type of processor is a Digital Signal Processor (DSP).

6. The multi-processor device according to claim 1, wherein the plurality of the first type of processors and the plurality of the second type of processors are controlled with separate clocks which differ in frequency or phase.

7. The multi-processor device according to claim 1, wherein, of the plurality of the first type of processors and the plurality of the second type of processors, the region of the plurality of the first type of processors is controlled with a high frequency clock and has closely spaced wiring of voltage supply lines, and the region of the plurality of the second type of processors is controlled with a low frequency clock and has sparse wiring of voltage supply lines.

8. The multi-processor device according to claim 1,

wherein, of the plurality of the first type of processors and the plurality of the second type of processors, the region of the plurality of the first type of processors is controlled with a high frequency clock, and the region of the plurality of the second type of processors is controlled with a low frequency clock, and

wherein the region of the first type of processors has a larger number of voltage supply terminals than the region of the second type of processors.

9. The multi-processor device according to claim 1, wherein, the CPU region and the external bus interface of the plurality of the first type of processors which are controlled with a high frequency clock, of the plurality of the first type of processors and the plurality of the second type of processors, are disposed far apart from each other over the single semiconductor chip.

10. The multi-processor device according to claim 9, wherein a high rate clock is supplied to the CPUs in the plurality of the first type of processors controlled with the high frequency clock, and a clock for the bus to which the external bus interface and processors for data processing are coupled is generated by gating a part of the clock.

11. The multi-processor device according to claim 1, wherein the plurality of the first type of processors and the plurality of the second type of processors operate using different operating systems.