Pre-distorting a transmitted signal for offset cancellation
First Claim
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1. A method comprising:
- generating an offset for a first clock phase of a multi-phase clock during a training interval in an offset driver based on an offset value generated in an offset logic, wherein the offset is varied during at least some iterations of the first clock phase and a data bit of an n-bit data is to be selected at the first clock phase;
transmitting the offset from a transmitter to a receiver along a link;
receiving an indication in the transmitter that a signal corresponding to the offset has been detected in the receiver with a predetermined density of a first logic level; and
storing an offset code in an offset register of the transmitter corresponding to the offset when the indication is received, the offset to correct an offset present in an interleaved receiver of the receiver corresponding to the first clock phase.
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Abstract
In one embodiment, the present invention includes a pre-driver to receive data of a first clock phase and to pre-drive the data, a driver coupled to the pre-driver to drive the data onto a link operable to be coupled to a receiver, and an offset driver to drive an offset value associated with the first clock phase onto the link with the data. Other embodiments are described and claimed.
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Citations
20 Claims
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1. A method comprising:
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generating an offset for a first clock phase of a multi-phase clock during a training interval in an offset driver based on an offset value generated in an offset logic, wherein the offset is varied during at least some iterations of the first clock phase and a data bit of an n-bit data is to be selected at the first clock phase; transmitting the offset from a transmitter to a receiver along a link; receiving an indication in the transmitter that a signal corresponding to the offset has been detected in the receiver with a predetermined density of a first logic level; and storing an offset code in an offset register of the transmitter corresponding to the offset when the indication is received, the offset to correct an offset present in an interleaved receiver of the receiver corresponding to the first clock phase. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. An apparatus comprising:
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a pre-driver to receive data based on a first clock phase of a multi-phase clock and to pre-drive the data; a driver coupled to the pre-driver to drive the data onto a link operable to be coupled to a receiver; an offset driver to drive an offset value associated with the first clock phase onto the link with the data, wherein the offset value is to correct an offset present in an interleaved receiver of the receiver corresponding to the first clock phase; and a termination resistance coupled to output nodes of the driver and the offset driver. - View Dependent Claims (11, 12, 13, 14, 15, 16)
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17. A system comprising:
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a transmitter including; a pre-driver to receive a datum of a multi-bit data based on a corresponding clock phase of a multi-phase clock and to pre-drive the datum, a driver coupled to the pre-driver to drive the datum onto a link at a transmission level, and an offset driver to drive an offset value associated with the corresponding clock phase onto the link with the datum; and a receiver coupled to the transmitter via the link, the receiver including; a plurality of interleaved receivers each to capture the datum and the offset value for one of the corresponding clock phases of the multi-phase clock, wherein the offset value is to correct an offset present in the interleaved receiver of the corresponding clock phase. - View Dependent Claims (18, 19, 20)
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Specification