Nonvolatile semiconductor memory device

• US 8,227,863 B2
• Filed: 03/20/2007
• Issued: 07/24/2012
• Est. Priority Date: 03/21/2006
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Asami, Yoshinobu, Takano, Tamae, Furuno, Makoto
• Primary Examiner(s): Lee, Eugene
• Application Number:
  US11/723,481
• Publication Number:
  US 20070221971A1
• Time in Patent Office: 1,953 Days
• Field of Search: 257/347, 257/314, 257/315
• US Class Current: 257/347
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1237 with a different composition, shape, layout or thickness of the gate insulator in different devices
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/49 comprising different types of peripheral transistor
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A semiconductor layer having a channel formation region provided between a pair of impurity regions spaced from each other is provided, and a first insulating layer a floating gate, a second insulating layer, and a control gate are provided above the semiconductor layer. The semiconductor material forming the floating gate preferably has a band gap smaller than that of the semiconductor layer. The band gap of a channel formation region in the semiconductor material forming the floating gate is preferably smaller than that of the semiconductor layer by 0.1 eV or more.

Claims

1. A semiconductor memory device comprising:

a semiconductor layer over a substrate, the semiconductor layer having a channel formation region between a pair of impurity regions formed apart from each other;

a first insulating layer over and in contact with an upper surface and a side surface of the semiconductor layer;

a floating gate over the channel formation region with the first insulating layer interposed therebetween;

a second insulating layer over the floating gate, the second insulating layer comprising a silicon nitride layer over the floating gate and a silicon oxide layer over the silicon nitride layer, wherein a thickness of the silicon nitride layer is smaller than a thickness of the silicon oxide layer; and

a control gate over the floating gate with the second insulating layer interposed therebetween,

wherein the semiconductor layer has a first region having a conductivity type which is different from a conductivity type of the pair of impurity regions,

wherein the first region extends from one of the pair of impurity regions to the other of the pair of impurity regions and is in contact with the channel formation region,

wherein the substrate is selected from the group of a glass substrate, a plastic substrate and a quartz substrate, and

wherein the floating gate includes a semiconductor material, a band gap of the semiconductor material is smaller than a band gap of the semiconductor layer.

2. The nonvolatile semiconductor memory device according to claim 1,

wherein the first insulating layer comprises a silicon oxide layer and a silicon nitride layer.

3. The nonvolatile semiconductor memory device according to claim 2,

wherein the floating gate is in contact with the silicon nitride layer.

4. The nonvolatile semiconductor memory device according to claim 2,

wherein the silicon oxide layer is formed by oxidizing the semiconductor layer by plasma treatment, and the silicon nitride layer is formed by nitriding the silicon oxide layer by plasma treatment.

5. The nonvolatile semiconductor memory device according to claim 1,

wherein a plurality of floating gates and control gates are arranged over the semiconductor layer.

6. The nonvolatile semiconductor memory device according to claim 1,

wherein difference between a band gap of the material forming the semiconductor layer and a band gap of a semiconductor material forming the floating gate is 0.1 eV or more.

7. The nonvolatile semiconductor memory device according to claim 1,

wherein an edge of the floating gate in a channel length direction extends beyond an edge of the control gate in a channel length direction.

8. The nonvolatile semiconductor memory device according to claim 1,

wherein the semiconductor layer has a low concentration impurity region of the same conductivity type as the pair of impurity regions, which overlaps with the floating gate.

9. The nonvolatile semiconductor memory device according to claim 1,

wherein an edge of the control gate in a channel length direction extends beyond an edge of the floating gate in a channel length direction.

10. A nonvolatile semiconductor memory device comprising:

a semiconductor layer over a substrate, the semiconductor layer having a channel formation region between a pair of impurity regions formed apart from each other;

a first insulating layer over and in contact with an upper surface and a side surface of the semiconductor layer;

a floating gate over the channel formation region with the first insulating layer interposed therebetween;

a second insulating layer over the floating gate, the second insulating layer comprising a silicon nitride layer over the floating gate and a silicon oxide layer over the silicon nitride layer, wherein a thickness of the silicon nitride layer is smaller than a thickness of the silicon oxide layer; and

a control gate over the floating gate with the second insulating layer interposed therebetween,

wherein the semiconductor layer has a first region having a conductivity type which is different from a conductivity type of the pair of impurity regions,

wherein the first region extends from one of the pair of impurity regions to the other of the pair of impurity regions and is in contact with the channel formation region,

wherein the substrate is selected from the group of a glass substrate, a plastic substrate and a quartz substrate, and

wherein the floating gate is formed from a material having a higher electron affinity than a material forming the semiconductor layer.

11. The nonvolatile semiconductor memory device according to claim 10,

wherein the first insulating layer comprises a silicon oxide layer and a silicon nitride layer.

12. The nonvolatile semiconductor memory device according to claim 11,

wherein the floating gate is in contact with the silicon nitride layer.

13. The nonvolatile semiconductor memory device according to claim 11,

wherein the silicon oxide layer is formed by oxidizing the semiconductor layer by plasma treatment, and the silicon nitride layer is formed by nitriding the silicon oxide layer by plasma treatment.

14. The nonvolatile semiconductor memory device according to claim 10,

wherein a plurality of floating gates and control gates are arranged over the semiconductor layer.

15. The nonvolatile semiconductor memory device according to claim 10,

wherein an edge of the floating gate in a channel length direction extends beyond an edge of the control gate in a channel length direction.

16. The nonvolatile semiconductor memory device according to claim 10,

wherein the semiconductor layer has a low concentration impurity region of the same conductivity type as the pair of impurity regions, which overlaps with the floating gate.

17. The nonvolatile semiconductor memory device according to claim 10,

wherein an edge of the control gate in a channel length direction extends beyond an edge of the floating gate in a channel length direction.

18. A nonvolatile semiconductor memory device comprising:

a semiconductor layer over a substrate, the semiconductor layer having a channel formation region between a pair of impurity regions formed apart from each other;

a first insulating layer over and in contact with an upper surface and a side surface of the semiconductor layer;

a floating gate over the channel formation region with the first insulating layer interposed therebetween;

a second insulating layer over the floating gate, the second insulating layer comprising a silicon nitride layer over the floating gate and a silicon oxide layer over the silicon nitride layer, wherein a thickness of the silicon nitride layer is smaller than a thickness of the silicon oxide layer; and

a control gate over the floating gate with the second insulating layer interposed therebetween,

wherein the semiconductor layer has a first region having a conductivity type which is different from a conductivity type of the pair of impurity regions,

wherein the first region extends from one of the pair of impurity regions to the other of the pair of impurity regions and is in contact with the channel formation region,

wherein the substrate is selected from the group of a glass substrate, a plastic substrate and a quartz substrate, and

wherein barrier energy formed by the first insulating layer for electrons of the floating gate is higher than barrier energy formed by the first insulating layer for electrons of the semiconductor layer.

19. The nonvolatile semiconductor memory device according to claim 18,

wherein the first insulating layer comprises a silicon oxide layer and a silicon nitride layer.

20. The nonvolatile semiconductor memory device according to claim 19,

wherein the floating gate is in contact with the silicon nitride layer.

21. The nonvolatile semiconductor memory device according to claim 19,

wherein the silicon oxide layer is formed by oxidizing the semiconductor layer by plasma treatment, and the silicon nitride layer is formed by nitriding the silicon oxide layer by plasma treatment.

22. The nonvolatile semiconductor memory device according to claim 18,

wherein a plurality of floating gates and control gates are arranged over the semiconductor layer.

23. The nonvolatile semiconductor memory device according to claim 18,

wherein an edge of the floating gate in a channel length direction extends beyond an edge of the control gate in a channel length direction.

24. The nonvolatile semiconductor memory device according to claim 18,

wherein the semiconductor layer has a low concentration impurity region of the same conductivity type as the pair of impurity regions, which overlaps with the floating gate.

25. The nonvolatile semiconductor memory device according to claim 18,

wherein an edge of the control gate in a channel length direction extends beyond an edge of the floating gate in a channel length direction.

26. A nonvolatile semiconductor memory device comprising:

a semiconductor layer over a substrate, the semiconductor layer having a channel formation region between a pair of impurity regions formed apart from each other;

a first insulating layer over and in contact with an upper surface and a side surface of the semiconductor layer;

a floating gate over the channel formation region with the first insulating layer interposed therebetween;

a second insulating layer over the floating gate, the second insulating layer comprising a silicon nitride layer over the floating gate and a silicon oxide layer over the silicon nitride layer, wherein a thickness of the silicon nitride layer is smaller than a thickness of the silicon oxide layer; and

a control gate over the floating gate with the second insulating layer interposed therebetween,

wherein the semiconductor layer has a first region having a conductivity type which is different from a conductivity type of the pair of impurity regions,

wherein the first region extends from one of the pair of impurity regions to the other of the pair of impurity regions and is in contact with the channel formation region,

wherein the substrate is selected from the group of a glass substrate, a plastic substrate and a quartz substrate, and

wherein the floating gate includes germanium or a germanium compound.

27. The nonvolatile semiconductor memory device according to claim 26,

wherein the first insulating layer comprises a silicon oxide layer and a silicon nitride layer.

28. The nonvolatile semiconductor memory device according to claim 27,

wherein the floating gate is in contact with the silicon nitride layer.

29. The nonvolatile semiconductor memory device according to claim 27,

wherein the silicon oxide layer is formed by oxidizing the semiconductor layer by plasma treatment, and the silicon nitride layer is formed by nitriding the silicon oxide layer by plasma treatment.

30. The nonvolatile semiconductor memory device according to claim 26,

wherein a plurality of floating gates and control gates are arranged over the semiconductor layer.

31. The nonvolatile semiconductor memory device according to claim 26,

wherein the germanium compound is a germanium oxide or a germanium nitride.

32. The nonvolatile semiconductor memory device according to claim 26,

wherein an edge of the floating gate in a channel length direction extends beyond an edge of the control gate in a channel length direction.

33. The nonvolatile semiconductor memory device according to claim 26,

wherein the semiconductor layer has a low concentration impurity region of the same conductivity type as the pair of impurity regions, which overlaps with the floating gate.

34. The nonvolatile semiconductor memory device according to claim 26,

wherein an edge of the control gate in a channel length direction extends beyond an edge of the floating gate in a channel length direction.

35. A nonvolatile semiconductor memory device comprising:

a semiconductor layer over a substrate, the semiconductor layer having a channel formation region between a pair of impurity regions formed apart from each other;

a first insulating layer over and in contact with an upper surface and a side surface of the semiconductor layer;

a floating gate over the channel formation region with the first insulating layer interposed therebetween;

a second insulating layer over the floating gate, the second insulating layer comprising a silicon nitride layer over the floating gate and a silicon oxide layer over the silicon nitride layer, wherein a thickness of the silicon nitride layer is smaller than a thickness of the silicon oxide layer; and

a control gate over the floating gate with the second insulating layer interposed therebetween,

wherein the semiconductor layer has a first region having a conductivity type which is different from a conductivity type of the pair of impurity regions,

wherein the first region extends from one of the pair of impurity regions to the other of the pair of impurity regions and is in contact with the channel formation region,

wherein the substrate is selected from the group of a glass substrate, a plastic substrate and a quartz substrate, and

wherein the floating gate is formed of germanium or a germanium compound to a thickness of from 1 nm to 10 nm, inclusive.

36. The nonvolatile semiconductor memory device according to claim 35,

wherein the first insulating layer comprises a silicon oxide layer and a silicon nitride layer.

37. The nonvolatile semiconductor memory device according to claim 36,

wherein the floating gate is in contact with the silicon nitride layer.

38. The nonvolatile semiconductor memory device according to claim 36,

wherein the silicon oxide layer is formed by oxidizing the semiconductor layer by plasma treatment, and the silicon nitride layer is formed by nitriding the silicon oxide layer by plasma treatment.

39. The nonvolatile semiconductor memory device according to claim 35,

wherein a plurality of floating gates and control gates are arranged over the semiconductor layer.

40. The nonvolatile semiconductor memory device according to claim 35,

wherein the germanium compound is a germanium oxide or a germanium nitride.

41. The nonvolatile semiconductor memory device according to claim 35,

wherein an edge of the floating gate in a channel length direction extends beyond an edge of the control gate in a channel length direction.

42. The nonvolatile semiconductor memory device according to claim 35,

wherein the semiconductor layer has a low concentration impurity region of the same conductivity type as the pair of impurity regions, which overlaps with the floating gate.

43. The nonvolatile semiconductor memory device according to claim 35,

wherein an edge of the control gate in a channel length direction extends beyond an edge of the floating gate in a channel length direction.