Patrol function used in flash storage controller to detect data errors

• US 8,245,101 B2
• Filed: 04/08/2008
• Issued: 08/14/2012
• Est. Priority Date: 12/27/2007
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Enterprise IP LLC (Western Digital Corporation)
• Inventors: Olbrich, Aaron K., Prins, Douglas A.
• Primary Examiner(s): MCCARTHY, CHRISTOPHER S
• Application Number:
  US12/082,204
• Publication Number:
  US 20090172499A1
• Time in Patent Office: 1,589 Days
• Field of Search: None
• US Class Current: 714/753
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 13/1657 Access to multiple memories
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1063 Control signal output circuits, e.g. status or busy flags, feedback command signals

Abstract

A patrol function performed in a storage controller connected to a flash memory storage module. The function causes selected areas of the flash storage to be read for purposes of detecting and correcting errors.

Claims

1. A method of managing data in a storage device which includes a controller and a flash memory module made up of a plurality of flash memory devices, the method comprising, when the storage device is operatively coupled to a host:

performing a first read which includes reading first data and first error correction code (ECC) information, wherein the plurality of flash memory devices are organized in groups each group of which including a plurality of areas, the first read being performed from a first area of a first group of flash memory devices, the first data being associated with a request from an initiator in the host, the initiator having an identifier associated therewith which is one of a plurality of identifiers stored in the storage device;

generating second ECC information relating to the first data; and

as a result of establishing that the first and second ECC information do not match, performing a first ECC correction operation on the first data and determining whether the first ECC correction was successful resulting in corrected first data and a value specifying the number of corrected errors, such that;

if the first ECC correction operation is successful but the number of corrected errors exceeds a threshold, writing the corrected first data to an area of the first group of flash memory devices other than the first area and setting an indicator indicating that the data contained in the first area is invalid and if the number of corrected errors is below or equals the threshold, discarding the corrected first data without writing the corrected first data to the flash memory module; and

if the first ECC correction operation is unsuccessful, performing a subsequent ECC correction operation, and if the subsequent ECC correction is not successful, sending an error message to the initiator associated with the first data using the identifier of the initiator associated to the first data.

2. The method as in claim 1, wherein

the first data further comprises first ECC information from a first area of a second group of flash memory devices;

and

performance of at least one method step in claim 1 for the first area of the first group of flash memory devices overlapping in time the performance of the same method step for the first area of the second group of flash memory devices.

3. The method as in claim 1, wherein the first data comprises data from substantially all areas of the first group of flash memory devices that contain valid data.

4. The method as in claim 1, further comprising:

repeating an ECC correction operation as a result of failure of a prior ECC correction operation;

when the repeated ECC correction operation is successful;

writing the corrected first data to an area of the first group of flash memory devices other than the first area of the first group of flash memory devices and setting an indicator indicating that the data contained in the first area of the first group of flash memory devices is invalid when the number of corrected errors exceeds the threshold; and

discarding the corrected first data without writing the corrected first data to the flash memory module when the number of corrected errors in the repeated ECC correction operation is below or equal to the threshold.

5. The method as in claim 4, further-comprising:

following failure of a prior ECC correction operation, reading the first data a second time and performing a first OR'"'"'ing operation that Ors together the results of the first read of the first data and the second read of the first data.

6. The method as in claim 5, further comprising:

following the first OR'"'"'ing operation, using the first ECC information to perform an ECC correction operation on the results of the first OR'"'"'ing operation, and, if the ECC correction operation on the results of the first OR'"'"'ing operation is successful;

writing the corrected first data to an area of the first group of flash memory devices other than the first area of the first group of flash memory devices and setting an indicator indicating that the data contained in the first area of the first group of flash memory devices is invalid when the number of corrected errors exceeds the threshold; and

discarding the corrected first data without writing the corrected first data to the flash memory module when the number of corrected errors in the repeated ECC correction operation does not exceed the threshold.

7. The method as in claim 6, further comprising:

as a result of an ECC correction operation on the results of the first OR'"'"'ing operation not being successful, performing a second OR'"'"'ing operation, using a third read of the first data and the results of the first OR'"'"'ing operation as inputs to the second OR'"'"'ing operation, and repeating the ECC correction operation using the results of the second OR'"'"'ing operation and the first ECC information.

8. The method as in claim 7 in which the failure of the ECC correction operation is due to the number of errors exceeding the number of errors that can be corrected in a single pass.

9. The method as in claim 1, wherein the controller includes a plurality of processors and the first read is performed using one of the plurality of processors.

10. The method as in claim 9, further comprising:

creating a processor worklist for the at least one of the plurality of processors selected by the initiator and determining whether the processor worklist contains one or more tasks; and

when the processor worklist contains one or more tasks, handling each of the one or more tasks-prior to performing the first read of first data.

11. The method as in claim 1, wherein the storage device further includes a host port circuit coupling the controller in the storage device and the initiator in the host.

12. A method of managing data in a storage controller comprising a plurality of processor circuits operatively coupled to a flash memory module made up of at least three flash memory groups the method comprising the following steps for each of the flash memory groups when the storage controller is operatively coupled to a host via a host port circuit:

checking to determine if a worklist associated with the flash memory group contains any tasks requested by an initiator in the host to execute a portion of a host command, the initiator having an identifier associated therewith which is one of a plurality of identifiers stored in the storage controller; and

performing the following steps if no tasks are found;

performing a flash memory read relating to an area of the flash memory group;

performing an ECC check related to data read from the area;

performing an action if the ECC check reveals errors;

repeating the above steps for substantially all areas of the flash memory group that contain currently valid data received as a result of a host-initiated write;

wherein at least one of the above steps is performed independently for each flash memory group; and

when an ECC correction performed after the repeated ECC checks is not successful, sending an error message to the initiator related to the data read from the area of the flash memory group using the identifier of the initiator stored in the storage controller.

13. The method as in claim 12, further comprising:

using ECC information to attempt to correct errors in the data read from the flash memory relating to an area of the flash memory group.

14. The method as in claim 13, further comprising:

writing the corrected data to the flash memory module when the action performed if the ECC check reveals errors is successful, the corrected data being written to the same flash memory group from which the uncorrected data was originally read, but to a different area from that group than the area from which the uncorrected data was originally read, the writing only occurring if the number of corrected errors exceeds a first threshold.

15. The method as in claim 14, wherein

the first threshold is less than the number of errors that can be corrected in a single ECC correction operation.

16. The method as in claim 15, further comprising

performing a second error correction operation using the ECC information when the action performed if the ECC check reveals errors is unsuccessful, and, if the second error correction operation is successful, writing the corrected data to the flash memory module, the corrected data being written to the same flash memory group from which the uncorrected data was originally read, but to a different area from that group than the area from which the uncorrected data was originally read, the writing only occurring if the number of corrected errors exceeds the first threshold.

17. The method as in claim 16, in which:

as a result of the second error correction operation being unsuccessful, OR'"'"'ing together the results of two or more flash memory reads and performing a third error correction operation using the ECC information and the results of the OR'"'"'ing operation, and, as a result of the third error correction operation being successful, writing the corrected data to the flash memory module, the corrected data being written to the same flash memory group from which the uncorrected data was originally read, but to a different area from that group than the area from which the uncorrected data was originally read, the writing only occurring if the number of corrected errors exceeds the first threshold.

18. The method as in claim 16, further including:

waiting until a specified event and, upon the specified event taking place,

checking to determine if a worklist associated with the flash memory group contains any tasks and performing the following steps if no tasks are found;

performing a flash memory read relating to an area of the flash memory group;

performing an ECC check related to data read from the area;

performing an action if the ECC check reveals errors;

repeating the above steps for substantially all areas of the flash memory group that contain currently valid data received as a result of a host-initiated write;

wherein

at least one of the above steps is performed independently for each flash memory group.

19. The method as in claim 18, in which:

the specified event is selected based at least in part on a value entered by a user of the system.

20. A method for managing data in a storage controller configured for operation in a system in which the storage controller comprises a plurality of processor circuits, the storage controller operatively coupled to a host via a host port circuit, the method comprising the following steps when the storage controller is operatively coupled to a flash memory module:

identifying an entry in a metadata table, the identification based on information in the entry, the information designating a first portion of the flash memory module;

reading first data and first ECC information associated with the entry, the first data being associated with a request by an initiator in the host, the initiator having an identifier included in a plurality of identifiers stored in the storage controller;

generating second ECC information based on the first data;

comparing the first and second ECC information;

if the first and second ECC information differ, performing a first ECC correction operation based on the first ECC information;

if the first ECC correction operation being is successful and if the number of errors corrected exceeds a threshold, writing the corrected data to the flash memory module and invalidating the entry;

wherein, if the number of errors corrected does not exceed the threshold, the corrected data is not written to the flash memory; and

if an ECC correction subsequent to the first ECC correction is unsuccessful, sending an error message to the initiator via the host port circuit using the identifier of the initiator associated with the first data.

21. The method as in claim 20, further including:

reading the first data a second time and performing a second ECC correction operation if the first ECC correction operation is unsuccessful, and, if the second ECC correction operation is successful and if the number of errors corrected exceeds a threshold, writing the corrected data to the flash memory module and invalidating the entry.

22. The method as in claim 21, further comprising:

a first operation of OR'"'"'ing together the results of the first read of the first data and the second read of the first data and using the results of the first OR'"'"'ing operation and the first ECC information as inputs to the second ECC correction operation.

23. The method as in claim 22, further including:

if the second ECC correction operation is not successful, reading the first data a third time and using the results of the first OR'"'"'ing operation and the third read of the first data as inputs to a second OR'"'"'ing operation;

using the results of the second OR'"'"'ing operation and the first ECC information as inputs to a third ECC correction operation; and

if the third ECC correction operation is successful and if the number of errors corrected exceeds a threshold, writing the corrected data to the flash memory module and invalidating the entry.

24. The method as in claim 23, further wherein all entries in the metadata table that contain information designating the first portion of the flash memory module are used.

25. The method as in claim 24, further wherein

all entries in the metadata table that contain information designating a second portion of the flash memory module are used, the performance of the steps for the first portion of the flash memory module overlapping the performance of the steps for the second portion of the flash memory module.

26. The method as in claim 25, further including:

checking a first worklist associated with the first portion of the flash memory module, delaying the identifying an entry in the metadata table if entries are present in the first worklist; and

checking a second worklist associated with the second portion of the flash memory module, delaying the identifying an entry in the metadata table if entries are present in the second worklist;

wherein the presence of entries on the first worklist does not affect performance of the method for the second portion of the flash memory module and the presence of entries on the second worklist does not affect performance of the method for the first portion of the flash memory module.

27. The method as in claim 26, further comprising:

waiting for a first designated event; and

performing the method steps in claim 26 using all entries designating the first portion of the flash memory module;

performing the method steps in claim 26 using all entries designating the second portion of the flash memory module.

28. The method as in claim 25 in which:

the first portion of the flash memory module consists of at least two flash dies, and the second portion of the flash memory module consists of at least two flash dies; and

the flash dies contained in the first portion of the flash memory module are different from the flash dies contained in the second portion of the flash memory module.

33. The storage controller of claim 23 wherein a first processor circuit related to the first data and a second processor circuit related to the second data are configured to operate independently of one another.

29. A storage controller operatively coupled to a host system and a flash memory module comprising:

a host port circuit to receive a host command from an initiator in the host system, the host command related to a first data in the flash memory module;

a plurality of processor circuits;

a memory circuit storing an identifier for the initiator; and

an error correction engine coupled to the selected processor circuit and configured to perform an ECC check for a first check data in the flash memory module,

wherein the error correction engine is configured to perform an error correction as a result of an error found by the ECC check, and

wherein the host port circuit is configured to send an error message to the initiator using the identifier as a result of the error correction not being successful.

30. The storage controller of claim 29 wherein the selected processor circuit is further configured to write a corrected data from the error correction engine to the flash memory module as a result of the number of errors detected by the error correction engine exceeding a threshold.

31. The storage controller of claim 29 wherein the error correction engine is configured to perform a subsequent error correction as a result of the error correction not being successful.

32. The storage controller of claim 29 wherein the host port circuit is configured to receive a second host command from a second initiator related to a second data in the flash memory module;

and

the storage controller further including

a second memory circuit storing a second identifier for the second initiator;

a second error correction engine coupled to the selected processor circuit related to the second data and configured to perform an ECC check for a second check data;

wherein

the error correction engine is configured to perform a second error correction as a result of an error found by the ECC check for the second check data; and

the host port circuit is configured to send an error message to the second initiator using the second identifier as a result of the second error correction not being successful.

34. The storage controller of claim 32 wherein the selected processor circuit related to the first data is the same as the selected processor circuit related to the second data.

35. The storage controller of claim 29 wherein the host port circuit is configured to receive a host command from a plurality of hosts.

36. The storage controller of claim 35 wherein the host port circuit is configured to receive a second host command from a second initiator related to a second data in the flash memory module;

and the storage controller further including

a second memory circuit storing a second identifier for the second initiator;

a second error correction engine coupled to the selected processor circuit related to the second data and configured to perform an ECC check for a second check data;

wherein

the error correction engine is configured to perform a second error correction as a result of an error found by the ECC check; and

the host port circuit is configured to send an error message to the second initiator using the second identifier as a result of the second error correction not being successful.

37. The storage controller of claim 36 wherein the selected processor circuit related to the first data and the selected processor circuit related to the second data are configured to operate independently of one another.

38. The storage controller of claim 36 wherein a first processor circuit related to the first data is the same as a second processor circuit related to the second data.

39. The storage controller of claim 36 wherein the first host command is related to a first host and the second host command is related to a second host.

40. The storage controller of claim 39 wherein the first host is the same as the second host.