Frequency doubler, a device including the same and a method for frequency doubling
First Claim
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1. A frequency doubler, comprising:
- a non-overlapping signal generation circuit configured to receive a first signal and a first control signal and generate a first and a second non-overlapping signal, each of the first and second non-overlapping signals having a frequency of the first signal, wherein an average of a duty cycle of the first non-overlapping signal and a duty cycle of the second non-overlapping signal is determined by the first control signal;
a combination circuit configured to receive and combine the two non-overlapping signals to generate a frequency-doubled signal;
wherein the non-overlapping signal generation circuit comprises;
an input module configured to receive the first signal and generate a first and a second clock signal according to the first signal;
a first controllable delay module configured to receive the first clock signal and the first control signal, apply a first delay determined at least partly by the first control signal to the first clock signal so as to generate a first delayed signal;
a second controllable delay module configured to receive the second clock signal and the first control signal, apply a second delay determined at least partly by the first control signal to the second clock signal so as to generate a second delayed signal;
wherein the input module is further configured to receive the first and second delayed signals and generate the first and second clock signals according to the first signal, the first delayed signals and the second delayed signal; and
an output module, configured to receive the first delayed signal and generate the first non-overlapping signal accordingly, receive the second delayed signal and generate the second non-overlapping signal accordingly.
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Abstract
A frequency doubler comprises: a non-overlapping signal generation circuit configured to receive a first signal and a first control signal and generate a first and second non-overlapping signals, each of the first and second non-overlapping signals has a frequency of the first signal, an average of a duty cycle of the first non-overlapping signal and a duty cycle of the second non-overlapping signal is determined by the first control signal; a combination circuit configured to receive and combine the two non-overlapping signals to generate a frequency-doubled signal.
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Citations
16 Claims
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1. A frequency doubler, comprising:
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a non-overlapping signal generation circuit configured to receive a first signal and a first control signal and generate a first and a second non-overlapping signal, each of the first and second non-overlapping signals having a frequency of the first signal, wherein an average of a duty cycle of the first non-overlapping signal and a duty cycle of the second non-overlapping signal is determined by the first control signal; a combination circuit configured to receive and combine the two non-overlapping signals to generate a frequency-doubled signal; wherein the non-overlapping signal generation circuit comprises; an input module configured to receive the first signal and generate a first and a second clock signal according to the first signal; a first controllable delay module configured to receive the first clock signal and the first control signal, apply a first delay determined at least partly by the first control signal to the first clock signal so as to generate a first delayed signal; a second controllable delay module configured to receive the second clock signal and the first control signal, apply a second delay determined at least partly by the first control signal to the second clock signal so as to generate a second delayed signal; wherein the input module is further configured to receive the first and second delayed signals and generate the first and second clock signals according to the first signal, the first delayed signals and the second delayed signal; and an output module, configured to receive the first delayed signal and generate the first non-overlapping signal accordingly, receive the second delayed signal and generate the second non-overlapping signal accordingly. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A frequency doubler, comprising:
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a non-overlapping signal generation circuit configured to receive a first signal and a first control signal and generate a first and a second non-overlapping signal, each of the first and second non-overlapping signals having a frequency of the first signal, wherein an average of a duty cycle of the first non-overlapping signal and a duty cycle of the second non-overlapping signal is determined by the first control signal; a combination circuit configured to receive and combine the two non-overlapping signals to generate a frequency-doubled signal; a first feedback circuit configured to receive the frequency-doubled signal and a first reference signal, use the frequency-doubled signal and the first reference signal to generate the first control signal; and
the first feedback circuit comprisinga first error amplifier configured to receive a first reference signal and the frequency-doubled signal, generate the first control signal according to an error between a voltage of the first reference signal and an average voltage of the frequency-doubled signal. - View Dependent Claims (9)
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10. A frequency doubler, comprising:
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a non-overlapping signal generation circuit configured to receive a first signal and a first control signal and generate a first and a second non-overlapping signal, each of the first and second non-overlapping signals having a frequency of the first signal, wherein an average of a duty cycle of the first non-overlapping signal and a duty cycle of the second non-overlapping signal is determined by the first control signal; a combination circuit configured to receive and combine the two non-overlapping signals to generate a frequency-doubled signal; and a duty cycle changing circuit configured to receive a second signal and change a duty cycle of the second signal to a preset value, so as to generate the first signal, the duty cycle changing circuit comprising a pulse generator configured to receive the second signal and use the second signal to generate a pulse sequence signal; a charge and discharge circuit configured to receive the pulse sequence signal and a second control signal, change a voltage at an output end of the charge and discharge circuit according to the pulse sequence signal at a speed which is at least partly determined by the second control signal; an analog-to-digital converter connected to the output end of the charge and discharge circuit and convert an output of the charge and discharge circuit from analog to digital, so as to generate the first signal. - View Dependent Claims (11, 12, 13, 14, 15, 16)
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Specification