Sequencing decoder circuit

• US 8,325,556 B2
• Filed: 10/07/2009
• Issued: 12/04/2012
• Est. Priority Date: 10/07/2008
• Status: Active Grant

• Current Assignee: JP Morgan Chase Bank, N.A. (JP Morgan Chase & Co)
• Original Assignee: Contour Semiconductor, Inc.
• Inventors: Shepard, Daniel R.
• Primary Examiner(s): NGUYEN, DANG T
• Application Number:
  US12/575,055
• Publication Number:
  US 20100085830A1
• Time in Patent Office: 1,154 Days
• Field of Search: 365/230.06, 365/239, 365/163, 365/51, 365/113, 365/115, 365/63, 365/105, 365/230.03, 365/230.08, 365/189.09, 365/189.05, 365/185.09, 365/230.01
• US Class Current: 365/230.06
• CPC Class Codes: G11C 8/10 Decoders

Abstract

A memory-array decoder operably coupled to a memory array comprising a sequence of rows and receiving as input a plurality of address bits includes first and second decoder stages. The first decoder stage selects one or more first rows by decoding a first subset of the address bits, and the second decoder stage selects one or more second rows based on locations, within the sequence, of one or more third rows different from the one or more second rows.

Claims

1. A memory-array decoder receiving as input a plurality of address bits and operably coupled to a memory array comprising a sequence of rows, the decoder comprising:

a first decoder stage for pre-charging a first group of one or more rows by decoding a first subset of the address bits; and

a second decoder stage for selecting one or more second rows based on locations, within the sequence, of one or more third rows different from the one or more second rows,

wherein the second decoder stage selects a selected row within the first group by decoding a second subset of the address bits, the selection of the selected row pre-charging a second group of one or more rows different from the first group.

2. The decoder of claim 1, wherein the first subset of the address bits and the second subset of the address bits are different.

3. The decoder of claim 2, wherein no address bits in the first subset are within the second subset.

4. The decoder of claim 1, wherein the second stage is capable of selecting the selected row from all rows in the memory array.

5. The decoder of claim 1, wherein the plurality of address bits comprises an input memory address and its complement.

6. The decoder of claim 1, wherein the memory array is programmed with data comprising at least one of music, video, computer software, a computer application, reference data, text, or a diagram.

7. The decoder of claim 1, wherein the decoder and memory array are disposed within a removable memory storage device.

8. The decoder of claim 1, wherein the memory array comprises a plurality of storage cells, at least one of which comprises a phase-change material.

9. A method of forming a memory-array decoder receiving as input a plurality of address bits and operably coupled to a memory array comprising a sequence of rows, the method comprising:

providing a first decoder stage for pre-charging a first group of one or more rows by decoding a first subset of the address bits; and

providing a second decoder stage for selecting one or more second rows based on locations, within the sequence, of one or more third rows different from the one or more second rows,

wherein the second decoder stage selects a selected row within the first group by decoding a second subset of the address bits, the selection of the selected row pre-charging a second group of one or more rows different from the first group.

10. A method of decoding a memory array comprising a sequence of rows, the method comprising:

receiving as input, by a decoder, a plurality of address bits;

pre-charging, with a first stage of the decoder, a first group of one or more rows by decoding a first subset of the address bits; and

selecting, with a second stage of the decoder, one or more second rows based on locations, within the sequence, of one or more third rows different from the one or more second rows,

wherein the second stage of the decoder selects a selected row within the first group by decoding a second subset of the address bits, the selection of the selected row pre-charging a second group of one or more rows different from the first group.

11. The method of claim 10, wherein the first subset of the address bits and the second subset of the address bits are different.

12. The method of claim 11, wherein no address bits in the first subset are within the second subset.

13. The method of claim 10, wherein the second stage is capable of selecting the selected row from all rows in the memory array.

14. The method of claim 10, wherein the plurality of address bits comprises an input memory address and its complement.