Power managed lock optimization
First Claim
1. A method comprising:
- a processor attempting to acquire a lock for a thread being executed;
responsive to failing to acquire the lock, determining that at least one additional iteration of attempting to acquire the lock is permitted for the thread, wherein the determining is responsive to an iteration count that is updated in response to each iteration of attempting to acquire the lock, wherein the iteration count indicates a number of permitted iterations of attempting to acquire the lock;
responsive to determining that the additional iteration is permitted, waiting for an event prior to initiating another iteration, wherein waiting for the event causes the processor to enter a low power state, reducing power consumption; and
responsive to determining that the additional iteration is permitted, permitting the thread to remain scheduled on the processor.
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Accused Products
Abstract
In an embodiment, a timer unit may be provided that may be programmed to a selected time interval, or wakeup interval. A processor may execute a wait for event instruction, and enter a low power state for the thread that includes the instruction. The timer unit may signal a timer event at the expiration of the wakeup interval, and the processor may exit the low power state in response to the timer event. The thread may continue executing with the instruction following the wait for event instruction. In an embodiment, the processor/timer unit may be used to implement a power-managed lock acquisition mechanism, in which the processor is awakened a number of times to check the lock and execute the wait for event instruction if the lock is not free, after which the thread may block until the lock is free.
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Citations
20 Claims
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1. A method comprising:
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a processor attempting to acquire a lock for a thread being executed; responsive to failing to acquire the lock, determining that at least one additional iteration of attempting to acquire the lock is permitted for the thread, wherein the determining is responsive to an iteration count that is updated in response to each iteration of attempting to acquire the lock, wherein the iteration count indicates a number of permitted iterations of attempting to acquire the lock; responsive to determining that the additional iteration is permitted, waiting for an event prior to initiating another iteration, wherein waiting for the event causes the processor to enter a low power state, reducing power consumption; and responsive to determining that the additional iteration is permitted, permitting the thread to remain scheduled on the processor. - View Dependent Claims (2, 3)
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4. A method comprising:
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a processor attempting to acquire a lock for a thread being executed; responsive to failing to acquire the lock, determining that at least one additional iteration of attempting to acquire the lock is permitted for the thread; responsive to determining that the additional iteration is permitted, waiting for an event prior to initiating another iteration, wherein waiting for the event causes the processor to enter a low power state, reducing power consumption; responsive to determining that the additional iteration is permitted, permitting the thread to remain scheduled on the processor; the processor detecting the event; the processor exiting the low power state; and the processor performing the additional iteration, wherein the performing the additional iteration comprises; the processor attempting to acquire the lock for the thread; responsive to failing to acquire the lock, determining that yet another iteration of attempting to acquire the lock is not permitted for the thread; and descheduling the thread. - View Dependent Claims (5)
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6. A computer accessible storage medium storing a plurality of instructions which, when executed by a processor, cause the processor to:
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attempt to acquire a lock for a thread being executed; responsive to failing to acquire the lock, determine that a reattempt to acquire the lock is permitted for the thread responsive to an iteration count that is updated in response to each iteration of attempting to acquire the lock, wherein the iteration count indicates a number of permitted iterations of attempting to acquire the lock; responsive to determining that the reattempt is permitted, wait for an event prior to initiating the reattempt, wherein the waiting causes the processor to enter a low power state; and responsive to determining that the reattempt is permitted, leave the thread scheduled on the processor. - View Dependent Claims (7, 8, 10)
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9. A computer accessible storage medium storing a plurality of instructions which, when executed by a processor, cause the processor to:
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attempt to acquire a lock for a thread being executed; responsive to failing to acquire the lock, determine that a reattempt to acquire the lock is permitted for the thread; responsive to determining that the reattempt is permitted, wait for an event prior to initiating the reattempt, wherein the waiting causes the processor to enter a low power state; responsive to determining that the reattempt is permitted, leave the thread scheduled on the processor; wherein the plurality of instructions include instructions executed in response to the processor detecting the event and exiting the lower power state, the instructions causing the processor to perform the reattempt, and wherein the instructions which, when executed, perform the reattempt comprise instructions which, when executed; attempt to acquire the lock for the thread; responsive to failing to acquire the lock, determine that yet another reattempt is not permitted for the thread; and block the thread.
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11. A method comprising:
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performing a plurality of iterations of; attempting to acquire a lock for a thread; and waiting for an event responsive to failing to acquire the lock, wherein waiting for the event causes the processor to enter a low power state, reducing power consumption; subsequent to performing the plurality of iterations without acquiring the lock, descheduling the thread. - View Dependent Claims (12, 13, 14, 15, 16)
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17. A computer accessible storage medium storing a plurality of instructions which, when executed by a processor, cause the processor to:
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perform a plurality of iterations of; attempting to acquire a lock for a thread; and waiting for an event responsive to failing to acquire the lock, wherein waiting for the event causes the processor to enter a low power state, reducing power consumption; subsequent to performing the plurality of iterations without acquiring the lock, block the thread. - View Dependent Claims (18, 19, 20)
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Specification