Dual bit line metal layers for non-volatile memory

• US 8,368,137 B2
• Filed: 06/26/2007
• Issued: 02/05/2013
• Est. Priority Date: 06/26/2007
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Mokhlesi, Nima, Wan, Jun
• Primary Examiner(s): Loke, Steven
• Assistant Examiner(s): Anya, Igwe U
• Application Number:
  US11/768,468
• Publication Number:
  US 20090003025A1
• Time in Patent Office: 2,051 Days
• Field of Search: 257/315, 257/E27.103
• US Class Current: 257/315
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Structures and techniques are disclosed for reducing bit line to bit line capacitance in a non-volatile storage system. The bit lines are formed at a 4ƒpitch in each of two separate metal layers, and arranged to alternate between each of the layers. In an alternative embodiment, shields are formed between each of the bit lines on each metal layer.

Claims

1. A non-volatile storage device, comprising:

a plurality of non-volatile storage elements formed in an array on a semiconductor substrate;

a plurality of parallel structures formed in at least two separate metal layers over the semiconductor substrate, wherein every other parallel structure in each metal layer defines a bit line and remaining parallel structures in each metal layer define shields and contact blocks such that each of the shields in each metal layer is formed in segments between the contact blocks along each alternating column of a plurality of columns of the array, wherein the bit lines and shields are formed to alternate between the metal layers, each of the bit lines being formed to have an alternating series of wider portions and narrower portions; and

a plurality of connections coupling the narrower portions of the bit lines and the storage elements.

2. The non-volatile storage device of claim 1, wherein the bit lines are formed at a pitch of 4ƒ

in each of the metal layers.

3. The non-volatile storage device of claim 1, wherein each of the shields formed in a first of the metal layers is connected to a ground potential and each of the shields formed in a second of the metal layers is connected to a source potential.

4. The non-volatile storage device of claim 1, wherein each of the shields is formed in segments between the connections.

5. The non-volatile storage device of claim 4, wherein the storage elements are organized into blocks, and one connection is formed for every two blocks of storage elements.

6. The non-volatile storage device of claim 1, wherein the wider portion of each bit line extends between each connection then narrows proximate to the connection.

7. The non-volatile storage device of claim 1, wherein the wider portion is twice as wide as the narrower portion.

8. The non-volatile storage device of claim 7, wherein the wider portion is approximately 120 nanometers wide and the narrower portion is approximately 60 nanometers wide.

9. A non-volatile storage device, comprising:

a plurality of non-volatile storage elements formed in an array on a semiconductor substrate;

a first plurality of structures formed in parallel in a first metal layer over the array, wherein every other parallel structure in the first metal layer defines a bit line and remaining parallel structures in the first metal layer define shields and contact blocks such that each of the shields in the first metal layer is formed in segments between the contact blocks along each alternating column of a plurality of columns of the array; and

a second plurality of structures formed in parallel in a second metal layer over the first metal layer, wherein every other parallel structure in the second metal layer defines a bit line and remaining parallel structures in the second metal layer define shields and contact blocks such that each of the shields in the second metal layer is formed in segments between the contact blocks along each alternating column of the plurality of columns of the array; and

a plurality of connections coupling the bit lines to corresponding storage elements of the plurality of non-volatile storage elements,

wherein the bit lines are formed to alternate between the first and second metal layers relative to the storage elements, and wherein each of the bit lines is formed to have a width that is narrower proximate to the connections and wider between the connections.

10. The non-volatile storage device of claim 9, wherein the array is organized into rows and columns of storage elements, and wherein adjacent columns are connected to respective bit lines in different metal layers.

11. The non-volatile storage device of claim 9, wherein:

the shields formed in the first metal layer are connected to a ground potential; and

the shields formed in the second metal layer are connected to a source potential.

12. The non-volatile storage device of claim 9, wherein each of the narrower width portions of the bit lines are aligned over the connections to the non-volatile storage elements, and the wider width portions extend between the connections.

13. A non-volatile storage system, comprising:

a plurality of non-volatile storage elements formed in an array on a semiconductor substrate, said array being organized into rows and columns;

a plurality of bit lines formed in a first metal layer over the array in correspondence with a first set of columns comprising every other column;

a plurality of shields and contact blocks formed in the first metal layer over the array in correspondence with a second set of columns comprising every other column not in the first set of columns such that each of the shields in the first metal layer is formed in segments between the contact blocks along the second set of columns of the array;

a plurality of bit lines formed in a second metal layer over the first metal layer in correspondence with the second set of columns comprising every other column not in the first set of columns;

a plurality of shields and contact blocks formed in the second metal layer over the first metal layer in correspondence with the first set of columns such that each of the shields in the second metal layer is formed in segments between the contact blocks along the first set of columns of the array; and

a plurality of connections coupling the bit lines and the storage elements such that adjacent columns are coupled to bit lines in different metal layers,

wherein each of the bit lines is continuous and tapers in to become narrower at the connections and tapers out to become wider between the connections.

14. The non-volatile storage system of claim 13, wherein the bit lines and shields are formed at a pitch of 2ƒ

relative to each other in each of the metal layers.

15. The non-volatile storage system of claim 13, wherein the metal layers are formed to be approximately 80 nanometers thick, and dielectric layers are formed between each metal layer to be approximately 250 nanometers thick.

16. The non-volatile storage system of claim 15, wherein the bit lines are formed to be approximately 60 nanometers wide, and spaced apart by a lateral distance of approximately 220 nanometers on center, in each metal layer.

17. The non-volatile storage system of claim 15, wherein a lateral distance between adjacent alternating bit lines is approximately 110 nanometers on center.