Methods of forming field effect transistors, methods of forming field effect transistor gates, methods of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, and methods of forming integrated circuitry comprising a transistor gate array including first gates and second grounded isolation gates

• US 8,389,363 B2
• Filed: 01/31/2011
• Issued: 03/05/2013
• Est. Priority Date: 02/02/2006
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Kim, Young Pil, Parekh, Kunal R.
• Primary Examiner(s): Malsawma, Lex
• Application Number:
  US13/017,508
• Publication Number:
  US 20110124168A1
• Time in Patent Office: 764 Days
• Field of Search: 438/257, 438/270, 257/E21.419
• US Class Current: 438/270
• CPC Class Codes: H01L 21/823456 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302

Abstract

The invention includes methods of forming field effect transistors, methods of forming field effect transistor gates, methods of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, and methods of forming integrated circuitry comprising a transistor gate array including first gates and second grounded isolation gates. In one implementation, a method of forming a field effect transistor includes forming masking material over semiconductive material of a substrate. A trench is formed through the masking material and into the semiconductive material. Gate dielectric material is formed within the trench in the semiconductive material. Gate material is deposited within the trench in the masking material and within the trench in the semiconductive material over the gate dielectric material. Source/drain regions are formed. Other aspects and implementations are contemplated.

Claims

1. A method of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, comprising:

forming masking material over semiconductive material of a substrate;

forming array circuitry trenches through the masking material and into the semiconductive material;

depositing array gate material within the array circuitry trenches in the masking material and within the array circuitry trenches in the semiconductive material;

after depositing the array gate material, forming peripheral circuitry trenches through the masking material;

depositing peripheral circuitry gate material within the peripheral circuitry trenches within the masking material;

the array circuitry trenches being formed using a masking step, and further comprising forming grounded gate trenches through the masking material in the array in the same masking step in which the array circuitry trenches are formed, the grounded gate trenches being formed into trench isolation material received within the substrate semiconductive material.

2. A method of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, comprising:

forming masking material over semiconductive material of a substrate;

forming array circuitry trenches through the masking material and into the semiconductive material;

depositing array gate material within the array circuitry trenches in the masking material and within the array circuitry trenches in the semiconductive material;

after depositing the array gate material, forming peripheral circuitry trenches through the masking material;

depositing peripheral circuitry gate material within the peripheral circuitry trenches within the masking material;

the peripheral circuitry trenches being formed using a masking step, and further comprising forming grounded gate trenches through the masking material in the array in the same masking step in which the peripheral circuitry trenches are formed, the grounded gate trenches being formed into trench isolation material received within the substrate semiconductive material.

3. A method of forming a field effect transistor, comprising:

forming masking material over semiconductive material of a substrate;

forming a trench through the masking material and into the semiconductive material;

forming gate dielectric material within the trench in the semiconductive material;

providing gate material within the trench in the masking material and within the trench in the semiconductive material over the gate dielectric material;

exposing sidewalls of the gate material outward of the semiconductive material;

forming insulative material over the sidewalls of the gate material outward of the semiconductive material;

anisotropically etching the insulative material to form insulative sidewall spacers over the sidewalls of the gate material outward of the semiconductive material;

forming source/drain regions; and

forming the gate material to comprise higher electrically conductive material received over lower electrically conductive material, said exposing of sidewalls of the gate material only being of sidewalls of the higher electrically conductive material.

4. A method of forming a field effect transistor, comprising:

forming masking material over semiconductive material of a substrate;

forming a trench through the masking material and into the semiconductive material;

forming gate dielectric material within the trench in the semiconductive material;

providing gate material within the trench in the masking material and within the trench in the semiconductive material over the gate dielectric material;

exposing sidewalls of the gate material outward of the semiconductive material;

forming insulative material over the sidewalls of the gate material outward of the semiconductive material;

anisotropically etching the insulative material to form insulative sidewall spacers over the sidewalls of the gate material outward of the semiconductive material;

forming source/drain regions; and

forming the gate material to comprise higher electrically conductive material received over lower electrically conductive material, the anisotropically etched sidewall spacers being formed over sidewalls of the higher electrically conductive material.

5. The method of claim 4 wherein the anisotropically etched sidewall spacers are not formed over sidewalls of the lower electrically conductive material.

6. A method of forming a field effect transistor, comprising:

forming masking material over semiconductive material of a substrate;

forming a trench through the masking material and into the semiconductive material;

forming gate dielectric material within the trench in the semiconductive material;

providing gate material within the trench in the masking material and within the trench in the semiconductive material over the gate dielectric material;

exposing sidewalls of the gate material outward of the semiconductive material;

forming insulative material over the sidewalls of the gate material outward of the semiconductive material;

anisotropically etching the insulative material to form insulative sidewall spacers over the sidewalls of the gate material outward of the semiconductive material;

forming source/drain regions;

forming the gate material to comprise higher electrically conductive material received over lower electrically conductive material, the anisotropically etched sidewall spacers being formed over sidewalls of the higher electrically conductive material;

capping the gate material with insulating material prior to said exposing; and

forming the anisotropically etched sidewall spacers over sidewalls of the insulating material.

7. A method of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, comprising:

forming masking material over semiconductive material of a substrate;

in a first masking step, forming array circuitry trenches through the masking material and into the semiconductive material and forming a first peripheral circuitry trench through the masking material;

depositing first gate material within the array circuitry trenches and the first peripheral circuitry trench;

in a second masking step, forming a grounded gate trench through the first gate material and the masking material within array area and forming a second peripheral circuitry trench through the first gate material and the masking material within area peripheral to the array area; and

depositing second gate material within the grounded gate trench and within the second peripheral circuitry trench.

8. A method of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, comprising:

forming masking material over semiconductive material of a substrate;

in a first masking step, forming array circuitry trenches through the masking material and into the semiconductive material;

depositing first gate material within the array circuitry trenches;

in a second masking step, forming a grounded gate trench through the first gate material and the masking material within array area and forming a first peripheral circuitry trench through the first gate material and the masking material within area peripheral to the array area;

depositing second gate material within the grounded gate trench and within the first peripheral circuitry trench;

in a third masking step, forming a second peripheral circuitry trench through the second gate material and through the first gate material within the peripheral area; and

depositing third gate material within the second peripheral circuitry trench.

9. The method of claim 8 wherein no trench is formed in the peripheral area using the first masking step.