Efficient use of hybrid media in cache architectures

• US 8,397,016 B2
• Filed: 12/31/2009
• Issued: 03/12/2013
• Est. Priority Date: 12/31/2008
• Status: Active Grant

• Current Assignee: Innovations In Memory LLC
• Original Assignee: Violin Memory Incorporated
• Inventors: Talagala, Nisha, Patterson, Martin, Bowen, James, Kercheval, Berry, Pernicka, Edward
• Primary Examiner(s): Dudek, Jr., Edward
• Assistant Examiner(s): Fishburn, John P
• Application Number:
  US12/650,966
• Publication Number:
  US 20110145479A1
• Time in Patent Office: 1,167 Days
• Field of Search: None
• US Class Current: 711/103
• CPC Class Codes: G06F 12/02 Addressing or allocation; Relocation program address sequencing G06F9/00; arrangements for selecting an address in a digital store G11C8/00
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0806 Multiuser, multiprocessor or multiprocessing cache systems
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 12/0897 with two or more cache hierarchy levels with multilevel cache hierarchies G06F12/0811
• CPC Class Codes: G06F 2212/225 Hybrid cache memory, e.g. having both volatile and non-volatile portions
• CPC Class Codes: G06F 2212/7211 Wear leveling

Abstract

A multi-tiered cache manager and methods for managing multi-tiered cache are described. Multi-tiered cache manager causes cached data to be initially stored in the RAM elements and selects portions of the cached data stored in the RAM elements to be moved to the flash elements. Each flash element is organized as a plurality of write blocks having a block size and wherein a predefined maximum number of writes is permitted to each write block. The portions of the cached data may be selected based on a maximum write rate calculated from the maximum number of writes allowed for the flash device and a specified lifetime of the cache system.

Claims

1. A multi-tiered cache system, comprising:

a plurality of cache elements including RAM and flash elements; and

a manager configured to control access to the cache elements,

wherein the manager causes cached data to be initially stored in the RAM elements and selects portions of the cached data stored in the RAM elements to be written to the flash elements based on at least a maximum write rate calculated from the maximum number of writes associated with the flash elements and a specified lifetime of the cache system,

wherein each RAM element is organized as a plurality of RAM blocks, and

wherein each of the portions of the cached data is moved when no RAM block is available for storing new data, and

wherein no RAM block is available when no available RAM block is large enough to store new cached data.

2. The system of claim 1, wherein each flash element is organized as a plurality of write blocks having a block size and wherein a predefined maximum number of writes is permitted for each write block.

3. The system of claim 1, wherein each of the portions of the cached data is moved to a designated write block and the portions of the cached data are substantially equal in size to the size of the designated write block.

4. The system of claim 1, wherein each RAM element is organized as a plurality of RAM blocks and wherein each of the portions of the cached data is moved when no RAM block is available for storing new data.

5. The system of claim 4, wherein RAM blocks are unavailable that contain cached data.

6. A method for managing mixed-media cache system, comprising:

receiving data for caching;

assigning the received data into one or more blocks;

optionally writing aged data stored in a RAM block to flash memory; and

storing the one or more blocks in RAM, wherein moving the aged data stored in the RAM block includes selecting the RAM block based on factors including the size of the one or more blocks and the age of the moved data, with a maximum write rate calculated from a maximum number of writes associated with flash memory elements and a specified lifetime of the cache system,

wherein each of the portions of the cached data is moved when no RAM block is available for storing new data, and

wherein no RAM block is available when no available RAM block is large enough to store new cached data.