Dynamically allocating number of bits per cell for memory locations of a non-volatile memory
First Claim
1. A method of accessing a memory location of a non-volatile memory device, the method comprising:
- dynamically allocating a first number of bits per cell to the memory location;
obtaining first data to store in the memory location, wherein the dynamically allocating is based on characteristics of the first data;
accessing the memory location based on the first number of bits per cell;
erasing the memory location;
dynamically assigning a second number of bits per cell to the memory location;
obtaining second data to store in the memory location subsequent to erasing the first data from the memory location, wherein the dynamically assigning is based on characteristics of the second data; and
accessing the memory location based on the second number of bits per cell.
1 Assignment
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Accused Products
Abstract
Systems and methods are provided for dynamically allocating a number of bits per cell to memory locations of a non-volatile memory (“NVM”) device. In some embodiments, a host may determine whether to store data in the NVM device using SLC programming or MLC programming operations. The host may allocate an erased block as an SLC block or MLC block based on this determination regardless of whether the erased block was previously used as an SLC block, MLC block, or both. In some embodiments, to dynamically allocate a memory location as SLC or MLC, the host may provide an address vector to the NVM package, where the address vector may specify the memory location and the number of bits per cell to use for that memory location.
10 Citations
20 Claims
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1. A method of accessing a memory location of a non-volatile memory device, the method comprising:
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dynamically allocating a first number of bits per cell to the memory location; obtaining first data to store in the memory location, wherein the dynamically allocating is based on characteristics of the first data; accessing the memory location based on the first number of bits per cell; erasing the memory location; dynamically assigning a second number of bits per cell to the memory location; obtaining second data to store in the memory location subsequent to erasing the first data from the memory location, wherein the dynamically assigning is based on characteristics of the second data; and accessing the memory location based on the second number of bits per cell. - View Dependent Claims (2, 3, 4, 5)
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6. A method of storing information in a non-volatile memory device, the method comprising:
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selecting an erased memory location of the non-volatile memory device in which to store the information; dynamically deciding on a number of bits per cell to use for the erased memory location, wherein the dynamically deciding comprises; determining at least one of a desired reliability, a desired storage speed, and a desired performance associated with the information; and deciding on the number of bits per cell to use based on the determining; and programming the information into the erased memory location of the non-volatile memory device based on the dynamically deciding. - View Dependent Claims (7, 8, 9, 10)
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11. A memory system comprising:
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a managed non-volatile memory (“
NVM”
) package comprising;at least one NVM device, and a NVM controller configured to access the at least one NVM device; and a host controller configured to direct the NVM controller to access a memory location of the at least one NVM device using an address vector, wherein the address vector indicates a number of bits per cell to use when accessing the memory location, and wherein the number of bits per cell to use when accessing the memory location is dynamically determined by the host controller based on characteristics of data associated with the memory location. - View Dependent Claims (12, 13, 14, 15, 16, 17)
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18. A memory system comprising:
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a raw non-volatile memory (“
NVM”
) package comprising;at least one NVM device comprising a plurality of blocks, an address input for receiving a selection of one of the plurality of blocks, and a single level cell/multi level cell (SLC/MLC) input for receiving an indication of a number of bits per cell associated with the one of the plurality of blocks selected through the address input; and a host controller operable to access at least one of the plurality of blocks using the address input and the SLC/MLC input, wherein the host controller dynamically determines the indication of the number of bits per cell based on data associated with the one of the plurality of blocks selected through the address input. - View Dependent Claims (19, 20)
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Specification