Filters for communication systems

• US 8,417,750 B2
• Filed: 10/13/2005
• Issued: 04/09/2013
• Est. Priority Date: 10/13/2004
• Status: Active Grant

• Current Assignee: MediaTek, Inc.
• Original Assignee: MediaTek, Inc.
• Inventors: Yan, Aiguo, Shabra, Ayman
• Primary Examiner(s): Yaary, Michael D
• Application Number:
  US11/249,930
• Publication Number:
  US 20060083297A1
• Time in Patent Office: 2,735 Days
• Field of Search: None
• US Class Current: 708/313
• CPC Class Codes: H03H 17/0657 where the output-delivery frequency is higher than the input sampling frequency, i.e. interpolation
• CPC Class Codes: H03H 17/0664 where the output-delivery frequency is lower than the input sampling frequency, i.e. decimation
• CPC Class Codes: H04L 25/03834 using pulse shaping

Abstract

The invention relates to a cascaded scheme in which an RRC filter, a modified RRC filter or other digital filter is implemented at a relatively low data rate, such as twice the symbol or chip rate, or 2×. Interpolation filters are used to increase the data rate to a higher data rate, such as 8×. Decimation filters are used to reduce the data rate from a higher rate, such as 8×, to a lower rate, such as 2×. The coefficients of the digital filter may be adjusted to compensate for characteristics of other components across the entire filter chain. Most of the implementation complexity of the filter chain is consolidated into the relatively low rate (such as 2×) digital filter while interpolation or decimation filters can be implemented at very low cost. The compensation capability provided by the digital filter makes design of simple decimation or interpolation filters much easier. The compensation capability provided by the digital filter, along with the relatively high over-sampling rate for the output of the interpolation filter (or the input of the decimation filter), also makes the design of the preceding (or following) analog filters much easier.

Claims

1. A root-raised-cosine filter chain circuit having an output at a first data rate, the filter chain circuit comprising:

a digital filter with programmable coefficients which operates at a second data rate that is lower than the first data rate; and

an interpolation filter connected in series with the digital filter and after the digital filter in the filter chain circuit, the interpolation filter configured to increase the data rate from the second data rate to the first data rate, wherein the coefficients of the interpolation filter are selected to introduce controlled distortions, and

wherein the programmable coefficients of the digital filter are selected to compensate for the controlled distortions introduced by the interpolation filter.

2. A root-raised-cosine filter chain circuit as defined in claim 1, wherein the digital filter comprises a modified Root-Raised-Cosine filter.

3. A root-raised-cosine filter chain circuit as defined in claim 1, wherein the digital filter is implemented in a digital processor and the interpolation filter is implemented in a mixed signal processor.

4. A root-raised-cosine filter chain circuit as defined in claim 1, wherein the second data rate is an integer multiple of a symbol or chip rate, the integer being greater than or equal to 2.

5. A root-raised-cosine filter chain circuit as defined in claim 1, wherein coefficients of the digital filter are selected also to compensate for characteristics of other components across the entire filter chain.

6. A root-raised-cosine filter chain circuit as defined in claim 1, wherein the digital filter includes a plurality of multipliers and the interpolation filter does not include any multiplier.

7. A root-raised-cosine filter chain circuit as defined in claim 1, wherein the first data rate is a multiple of a symbol rate in a wireless communication system.

8. A root-raised-cosine filter chain circuit as defined in claim 1, wherein the first data rate is a multiple of a chip rate in a wireless communication system.

9. A root-raised-cosine filter chain circuit as defined in claim 1, wherein the digital filter and the interpolation filter are located on a digital baseband processor of a wireless communication system.

10. A filter chain circuit as defined in claim 5 wherein the other components include at least one of an analog to digital converter (ADC), a decimation filter and an analog filter.

11. A filter chain circuit as defined in claim 1 wherein the coefficients of the interpolation filter are of the form ±

2^m±

2ⁿ, wherein m and n are positive or negative integers or zero.

12. A filter chain circuit as defined in claim 11 wherein at least some of the coefficients of the interpolation filter have values including 1, 1+½

, 2−

¼ and

−

3.

13. A root-raised-cosine filter chain circuit as defined in claim 1, further comprising an analog to digital converter (ADC) that provides a digital output at a third data rate wherein the third data rate is less than the first data rate and greater than the second data rate.

14. A root-raised-cosine filter chain circuit as defined in claim 13, further comprising a decimation filter, connected in series between the ADC and the digital filter, that decreases the data rate from the third data rate to the second data rate.

15. A method for filtering a signal in a root-raised-cosine filter chain circuit and providing an output at a first data rate, comprising:

filtering the signal in a digital filter with programmable coefficients at a second data rate that is lower than the first data rate; and

filtering the output of the digital filter in an interpolation filter that increases the data rate from the second data rate to the first data rate,

wherein the coefficients of the interpolation filter are selected to introduce controlled distortions and wherein the programmable coefficients of the digital filter are selected to compensate for the controlled distortions introduced by the interpolation filter.

16. A method as defined in claim 15, wherein multiplications are not performed in the interpolation filtering step.

17. A method as defined in claim 15, further comprising programming the programmable coefficients of the digital filter.

18. A method as defined in claim 17, further comprising programming the programmable coefficients of the digital filter to also compensate for characteristics of other components across an entire filter chain.

19. A method as defined in claim 18, further comprising transmitting data between the digital filter and the interpolation filter at a relatively low data rate as compared to data rates at inputs of other digital filters in the filter chain.

20. A method as defined in claim 18 wherein the other components include at least one of an analog to digital converter (ADC), a decimation filter and an analog filter.

21. A root-raised-cosine filter chain circuit having an input at a first data rate, comprising:

a decimation filter which receives the input at the first data rate and decreases the data rate from the first data rate to a second data rate that is lower than the first data rate, wherein the coefficients of the decimation filter are selected to introduce controlled distortions; and

a digital filter with programmable coefficients connected in series with the decimation filter, wherein the digital filter operates at the second data rate,

wherein the programmable coefficients of the digital filter are configured to compensate for the controlled distortions introduced by the decimation filter.

22. A root-raised-cosine filter chain circuit as defined in claim 21, wherein the digital filter comprises a modified Root-Raised-Cosine filter.

23. A root-raised-cosine filter chain circuit as defined in claim 21, wherein the digital filter is implemented in a digital processor and the decimation filter is implemented in a mixed signal processor.

24. A root-raised-cosine filter chain circuit as defined in claim 21, wherein the second data rate is an integer multiple of a symbol or chip rate, the integer being greater than or equal to 2.

25. A root-raised-cosine filter chain circuit as defined in claim 21, wherein the digital filter and the decimation filter are implemented on separate integrated circuits and wherein the decimation filter communicates with the digital filter at the lowest sampling rate which is an integer multiple of a symbol or chip rate.

26. A root-raised-cosine filter chain circuit as defined in claim 21, wherein coefficients of the digital filter are selected to also compensate for characteristics of other components across the entire filter chain.

27. A root-raised-cosine filter chain circuit as defined in claim 21, wherein the digital filter includes a plurality of multipliers and the decimation filter does not include any multiplier.

28. A root-raised-cosine filter chain circuit as defined in claim 21, wherein the first data rate is a multiple of a symbol rate in a wireless communication system.

29. A root-raised-cosine filter chain circuit as defined in claim 21, wherein the first data rate is a multiple of a chip rate in a wireless communication system.

30. A root-raised-cosine filter chain circuit as defined in claim 21, wherein the digital filter is located on a digital baseband processor of a wireless communication system and the decimation filter is located on an analog baseband processor of the wireless communication system.

31. A filter chain circuit as defined in claim 26 wherein the other components include at least one of an analog to digital converter (ADC), an interpolation filter and an analog filter.

32. A filter chain circuit as defined in claim 21 wherein the coefficients of the decimation filter are of the form ±

2^m±

2ⁿ, wherein m and n are positive or negative integers or zero.

33. A filter chain circuit as defined in claim 32 wherein at least some of the coefficients of the decimation filter have values including 1, 2, 1+ 1/2 and −

3.

34. A root-raised-cosine filter chain circuit as defined in claim 21, further comprising an interpolation filter that increases the data rate from the second data rate to a third data rate wherein the third data rate is different from the first data rate.

35. A method for filtering an input signal in a root-raised-cosine filter chain circuit at a first data rate, comprising:

filtering the input signal in a decimation filter that decreases the data rate from the first data rate to a second data rate that is lower than the first data rate; and

filtering the output of the decimation filter in a digital filter with programmable coefficients at the second data rate,

wherein the coefficients of the decimation filter are selected to introduce controlled distortions and wherein the programmable coefficients of the digital filter are selected to compensate for the controlled distortions introduced by the decimation filter.

36. A method as defined in claim 35, wherein multiplications are not performed in the decimation filtering step.

37. A method as defined in claim 35, further comprising programming the programmable coefficients of the digital filter.

38. A method as defined in claim 37, further comprising programming the programmable coefficients of the digital filter to also compensate for characteristics of other components across an entire filter chain.

39. A method as defined in claim 38, further comprising transmitting data between the decimation filter and the digital filter at a relatively low data rate as compared to data rates at inputs of other digital filters in the filter chain.

40. A method as defined in claim 38 wherein the other components include at least one of an analog to digital converter (ADC), an interpolation filter and an analog filter.

41. A root-raised-cosine filter chain circuit having an output at a first data rate, the filter chain circuit comprising:

a digital filter with programmable coefficients which operates at a second data rate that is lower than the first data rate;

a timing adjustment module connected in series with the digital filter to decrease the second data rate received from the digital filter to a third data rate; and

an interpolation filter connected in series with the timing adjustment module and after the digital filter in the filter chain circuit, the interpolation filter configured to increase the data rate from the third data rate to the first data rate, wherein the coefficients of the interpolation filter are selected to introduce controlled distortions, and

wherein the programmable coefficients of the digital filter are selected to compensate for the controlled distortions introduced by the interpolation filter.

42. A root-raised-cosine filter chain circuit as defined in claim 41 wherein the timing adjustment module and the digital filter are implemented on a digital integrated circuit and the interpolation filter is implemented on a mixed signal integrated circuit.

43. A root-raised-cosine filter chain circuit as defined in claim 42 wherein the digital filter communicates with the interpolation filter at the lowest sampling rate which is an integer multiple of a symbol or chip rate.

44. A root-raised-cosine filter chain circuit as defined in claim 41, wherein the digital filter is located on a digital baseband processor of a wireless communication system and the interpolation filter is located on a mixed signal baseband processor of the wireless communication system.

45. A root-raised-cosine filter chain circuit as defined in claim 41, wherein a digital to analog converter (DAC) is connected to the output of the filter chain.

46. A root-raised-cosine filter chain circuit as defined in claim 45, wherein the programmable coefficients of the digital filter are also selected to compensate for the distortions introduced by the DAC.