Efficient reloading of data into cache resource
First Claim
1. An apparatus, comprising:
- cache lines configured to store copies of data from a storage target; and
logic circuitry configured to invalidate the cache lines when the copies of the data in the cache resource may be inconsistent with the data in the storage target, the logic circuit further configured to identify addresses for at least some cache lines that were previously valid and reload copies of the data at the identified addresses from the storage target into some of the cache lines.
12 Assignments
0 Petitions
Accused Products
Abstract
A storage proxy includes a cache resource. A processor is configured to receive read and write requests sent from an initiator to a target over a first proxy path. The processor invalidates the cache lines when the read and write requests are redirected over a second direct path between the initiator and the target or when some other event indicates the data in the cache lines may no longer be consistent with corresponding data in the target. The processor identifies addresses for at least some of the cache lines that were previously valid and reloads the data for the identified addresses from the target back into some the cache lines when the read and write requests are redirected back over the first proxy path or when consistency can resumed between the data in the cache lines and corresponding data in the target.
-
Citations
22 Claims
-
1. An apparatus, comprising:
-
cache lines configured to store copies of data from a storage target; and logic circuitry configured to invalidate the cache lines when the copies of the data in the cache resource may be inconsistent with the data in the storage target, the logic circuit further configured to identify addresses for at least some cache lines that were previously valid and reload copies of the data at the identified addresses from the storage target into some of the cache lines. - View Dependent Claims (2, 3, 4, 5, 6, 8, 9, 10)
-
-
7. The apparatus according 1 wherein the logic circuitry is configured to:
-
identify a first address associated with a first previously valid cache line; identify an address range that includes the first address; identify a second address associated with a second previously valid cache line; extend the address range to include the second address when a gap between the first address and the second address range is under a threshold; and extend the address range to only include the second address when a gap between the first address and the second address range is over a threshold.
-
-
11. A computer readable medium containing instructions configured to be executed by a computer system, the instructions when executed by the computer system comprising:
-
loading data from a storage disk into cache lines in a cache resource; invalidating the cache lines when a condition is detected where consistency might not be maintained between the data in the cache resource and corresponding data in the storage disk; identifying addresses for previously valid cache lines; and reloading data corresponding with the addresses from the storage disk into some of the cache lines when consistency can be maintained between the data in the cache resource and the corresponding data in the storage disk. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18)
-
-
19. A storage proxy, comprising:
-
a cache resource including cache lines; and a processor configured to receive storage access requests sent over a first proxy path from an initiator to a target and invalidate the cache lines when the storage access requests are redirected over a second direct path between the initiator and the target, the processor further configured to identify addresses for at least some of the cache lines that were previously valid and reload the data from the target at the identified addresses into some of the cache lines. - View Dependent Claims (20, 21, 22)
-
Specification